DAMC-FMC2ZUP User’s Manual
DAMC-FMC2ZUP Architecture
12
2.
DAMC-FMC2ZUP Architecture
This chapter offers a technical overview of the many features implemented on
this board.
2.1
Functional Block Diagram
This section presents the block diagram of the connectivity implemented on the
board, excluding the clock network which is described in the next section. In the
following paragraphs are described the connections with the backplane, with
FMC/FMC+ connectors and with Zone3.
2.1.1
MicroTCA backplane
The following interconnections are available over the MicroTCA backplane:
Gigabit Ethernet (ports 0 and 1):
GbE interface on Port 0 is provided through a specialized RGMII to Ethernet
1000-baseX IC to guarantee fully compliance to the MicroTCA standard. The RGMII
communication is under control of the PS, thus allowing an easy implementation of
the required protocol stacks in software. The redundant GbE interface on Port 1 is
connected to Multi-Gigabit Transceiver (MGT) on the PL and can be used as a SGMII
interface to communicate with the redundant MCH.
SATA (ports 2 and 3):
Serial-ATA interfaces are directly connected to the PS MGTs. This gives the
user flexibility to store data from an Operating System running on the ARM Cores to
a Hard Disk Drive (HDD) or Solid-State Disk (SSD) residing on another AMC card.
For further details on this interface please refer to the backplane connectivity manual.
Содержание DAMC-FMC2ZUP
Страница 14: ...DAMC FMC2ZUP User s Manual DAMC FMC2ZUP Architecture 14 Figure 2 1 Block Diagram...
Страница 19: ...DAMC FMC2ZUP User s Manual DAMC FMC2ZUP Architecture 19 Figure 2 2 Clock Network Diagram...
Страница 33: ...DAMC FMC2ZUP User s Manual Appendix 33 Figure 5 6 FMC connections...
Страница 34: ...DAMC FMC2ZUP User s Manual Appendix 34 Figure 5 7 FMC connections...
