CAENels DAMC-FMC2ZUP, Руководство пользователя

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DAMC-FMC2ZUP User’s Manual DAMC-FMC2ZUP Architecture
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PCIe over Fat Pipe (ports 4 to 7):
PCIe x4 Gen.3 (Gen.4 can be enabled but is not officially supported)
connectivity is achieved using the Hard IP blocks located in the PL area of the FPGA.
Connecting these ports to the PL MGTs instead of the PS ones offer many benefits
among which a higher data throughput (PS MGTs are limited to PCIe Gen.2). This
interface can be expanded to provide a x8 lanes link when ports 4 to 11 (Fat Pipe and
Extended Fat Pipe) are used in systems that support this configuration
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.
Extended Fat Pipe (ports 8 to 11):
Ports 8 to 11 are routed to a dedicated MGT Quad on the PL section of the
FPGA. These lanes can be used to extend the PCIe interface or to implement any
other supported protocol (restrictions may apply depending on MicroTCA system
configuration).
Low Latency Links (ports 12 to 15):
As for the previous link these ports are also routed to a dedicated MGT Quad
of the PL. These lanes are usually implemented on the MicroTCA backplane as
board-to-board links and their usage is user’s application dependent.
M-LVDS (ports 17 to 20):
Ports 17 to 20 are implemented using specialized ICs and are accessible from
the PL section of the Main FPGA. The enable signal of the transmitters is under
control of the FPGA itself (optional factory configuration where RX19, TX19 and
RX20 transmitters are always disabled). Read-back of the MLVDS lanes is always
enabled and available to the FPGA logic.
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x8 links are not possible on systems with redundant MCHs due to the non-transparent nature of the
PCIe switches in the bus enumeration process