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CAEN

Electronic Instrumentation

UM5175

–

V2495/VX2495 User Manual rev. 1

57

11.7

Gate and Delay Demo Description

Introduction

In this demo the functionalities and use of the Gate and Delay Generator will be shown. The signal to be delayed can be
selected between an internally-generated clock of configurable frequency (submultiples of 50 MHz) and the input from
the G0 connector (please refer to Sect.

Gate and Delay Controller

for the G0 and G1 port configuration required in this

case). An output signal of configurable width and

delay with respect to the input signal’s leading edge will be available

on G1.

Register Map

In this example, 3 registers are used, 1 of which (MONITOR register) can be only read and 2 (CONTROL registers) can be
both read and written. All registers are 32-bit wide and can be accessed in single access mode

.

ADDRESS

REGISTER/CONTENT

ACCESS MODE

Read/Write

Base + 0x1000
Base + 0x1800
Base + 0x1804

Firmware Version
Control register
Clock frequency register

A24/A32
A24/A32
A24/A32

D16/D32
D16/D32
D16/D32

R
R/W
R/W

The registers of the Gate and Delay controller are used to configure the GDG parameters.

ADDRESS

REGISTER/CONTENT

ACCESS MODE

Read/Write

Base + 0x7F00
Base + 0x7F04
Base + 0x7F08
Base + 0x7F0C
Base + 0x7F10

Data write register
Command register
Control register
Data read register
Status register

A24/A32
A24/A32
A24/A32
A24/A32
A24/A32

D16/D32
D16/D32
D16/D32
D16/D32
D16/D32

R/W
R/W
R/W
R
R

Register Description

➢

FIRMWARE VERSION register:

Stores the revision number of the firmware.

Address:

0x1000.

Mode:

Read only.

Bit

Description

[31:0]

Revision Number

➢

CONTROL register:

Address:

0x1800.

Mode:

Read and Write.

Bit

Description

[8:4]

The DFPGA channel used to delay the input signal

[1]

Input signal selection:
0 = clock signal (frequency set by bits [8:4]
1 = G0 input

[0]

I/O port level selection:
0 = NIM level
1 = TTL level

WARNING:

When the G0 connector is used as an input, the user should follow the procedure described in Sect.

User FPGA I/O ports

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Содержание V2495

Страница 1: ...CAEN Tools for Discovery n Electronic Instrumentation User Manual UM5175 V2495 VX2495 VME Programmable Logic Unit Rev 1 October 11th 2018 ...

Страница 2: ...8500 0x8AFF Sect Introduction Chap 12 Symbols Abbreviated Terms and Notation AM Address Modifier FPGA Field Programmable Gate Array GA Geographical Address GDG Gate and Delay Generator LB Local Bus LBM Local Bus Master LBS Local Bus Slave LED Light Emitting Diode MFPGA Main FPGA SPI Serial Peripheral Interface SW Switch UFPGA User FPGA USB Universal Serial Bus VBA VME Base Address VME Versa Module...

Страница 3: ...sumed for inaccuracies CAEN SpA reserves the right to modify its products specifications without giving any notice for up to date information please visit www caen it MADE IN ITALY We stress the fact that all the boards are made in Italy because in this globalized world where getting the lowest possible price for products sometimes translates into poor pay and working conditions for the people who...

Страница 4: ...g 23 7 4 Setting the VME Base Address 24 7 5 Selecting the User FPGA Firmware 24 7 6 Power on Configuration Sequence 25 Boot Mode Selection 25 8 Driver and Software Installation 26 8 1 Drivers 26 Direct USB Driver 26 VME Access 29 8 2 Software Tools 30 CAENUpgrader 30 PLULib Library 33 9 Communication Interfaces 34 9 1 VME Bus 34 9 2 USB 34 9 3 Address Map 35 User FPGA Data Access 0x0000 0x0FFF 35...

Страница 5: ...g 4 1 Front panels view 13 Fig 5 1 On board internal connectors and LEDs 16 Fig 7 1 V2495 motherboard with mezzanine boards 22 Fig 7 2 Multi pin connector pin assignment 23 Fig 7 3 CAEN A967 Cable Adapter 23 Fig 7 4 Base Address on board rotary switches 24 Fig 7 5 User Firmware rotary switch 24 Fig 7 6 Boot mode jumper for the Main FPGA 25 Fig 8 1 V2495 hardware detection 26 Fig 8 2 USB driver man...

Страница 6: ...20 Tab 9 1 V2495 register address map 35 Tab 9 2 VME interface registers 36 Tab 9 3 ROM Address Map of the V2495 37 Tab 9 4 CSR registers 38 Tab 10 1 Clock ports description table 40 Tab 10 2 Mainboard Robinson Nugent connector description table 40 Tab 10 3 LEMO G ports description table 40 Tab 10 4 Expansion I O ports description table 41 Tab 10 5 A395D mapping 41 Tab 10 6 LED ports description t...

Страница 7: ...ATING MAY DAMAGE THE MODULE refer to Chap 6 CAUTION this product needs proper handling V2495 DOES NOT SUPPORT LIVE INSERTION HOT SWAP TAKE CARE OF REMOVING OR INSERTING THE BOARD WHEN THE VME CRATE IS POWERED OFF CAEN provides the specific document Precautions for Handling Storage and Installation available in the documentation tab of the product s web page The user is required to read this manual...

Страница 8: ...e board can be controlled and programmed through either the VME or the USB interface The CAENUpgrader software tool is provided to upload the FPGA firmware An onboard dedicated JTAG connector allows for in system JTAG configuration and debugging e g using Altera SignalTap The V2495 can be considered as an evolution of CAEN V1495 board with which it bears several analogies e g the front panel conne...

Страница 9: ...PCI Bridge WVX2718XAAAA VX2718LC VX2718LC VME PCI Bridge WVX2718LCXAA V2718LC KIT V2718KITLC VME PCI Bridge V2718 PCI Optical Link A2818 Optical Fibre 5m duplex AY2705 Rohs WK2718LCXAAA V2718 KIT V2718KIT VME PCI Bridge V2718 PCI OpticalLink A2818 Optical Fibre 5m duplex AY2705 WK2718XAAAAA V2718 KIT B V2718KITB VME PCI Bridge V2718 PCIe Optical Link A3818A Optical Fibre 5m duplex AY2705 WK2718XBA...

Страница 10: ...umentation UM5175 V2495 VX2495 User Manual rev 1 10 2 Block Diagram A B C 32 32 32 32 32 32 USER PROGRAMMABLE FPGA UFPGA MAIN FPGA MFPGA 16 bit VME BUS LOCAL BUS G Gate and Delay Generator D E F USB 32 Fig 2 1 Block diagram ...

Страница 11: ...X Main FPGA Cyclone V E Gate and Delay Generator Local Bus 16 bit 50MHz USB PHY VME BUS P1 P2 FLASH FLASH FLASH A PORT IN D PORT IN OUT B PORT IN E PORT IN OUT C PORT OUT F PORT IN OUT USB G PORT IN OUT JTAG JTAG P1 P2 USER FW SELECTOR 50 MHz 50 MHz 50 MHz AD9520 VME BASE ADDRESS SELECTORS Fig 3 1 Main components and interconnections ...

Страница 12: ...lash memory can store a set of firmware images to be loaded on the User FPGA A dedicated JTAG connector allows to program the UFPGA on the fly for fast firmware prototyping and debugging 3 5 Gate and Delay Generator The V2495 hosts a Gate and Delay Generator see Fig 3 2 able to provide up to 32 gated and delayed signals delayed signals triggered by 32 inputs start signals The gate width and delay ...

Страница 13: ...bels USB PORT VME DATA ACKNOWLEDGE LED CONFIGURATION LED A CONNECTOR 32 ch input only USB ACTIVITY LED USER CONFIGURATION LEDs B CONNECTOR 32 ch input only C CONNECTOR 32 ch output only G0 G1 CONNECTORS Input Output selectable Fig 4 1 Front panels view V2495 and VX2495 have the same front panel and connectors ...

Страница 14: ...lights up if a USB read write access to the board is performed DTACK LED FUNCTION This LED lights up whenever a VME read write access to the board is performed COLOR Green A B C CONNECTORS FUNCTION Motherboard I O 34 34 pin connectors A B are inputs C is an output ELECTRICAL SPECS See Tab 6 1 MECHANICAL SPECS Series 80 0009 0666 1 Type P50E 068 P1 SR1 TG Manufacturer 3M CFG LED FUNCTION This LED i...

Страница 15: ... Series 00 LEMO Connectors Type EPY 00 250 NTN Manufacturer LEMO 0 1 2 7 LEDs FUNCTION The status of these LEDs is user programmable NOTE when the UFPGA is in Factory mode odd and even LEDs alternatively blink COLOR Green LABELS Two blue labels on each insertion extraction handle of the VME front panel report Manufacturer name and board s model Brief functional description The label at the bottom ...

Страница 16: ...X2495 User Manual rev 1 16 5 Internal Connectors and LEDs UFPGA JTAG MFPGA JTAG MEZZANINE SOCKETS UFPGA CONF_DONE LED MFPGA CONF_DONE LED GDG CONF_DONE LEDs POWER SUPPLY LEDS G PORT TERMINATION SWITCHES Fig 5 1 On board internal connectors and LEDs ...

Страница 17: ...s 7610 6002 Board Connector Type 7610 6002 5 5 DR Manufacturer 3M MEZZANINE SOCKET FUNCTION Mezzanine board expansion connector x3 ELECTRICAL SPECS N A MECHANICAL SPECS Series Stacking Board Connectors Type 61083 104400LF Manufacturer AMPHENOL FCI G PORTS TERMITNATION SWITCHES FUNCTION Two switches one for each G connector enable or disable the 50 Ω termination according to the input or output dir...

Страница 18: ...ights up when the User FPGA is properly programmed COLOR Green GDG CONF_DONE LEDs FUNCTION Two LEDs indicate the status of the Gate and Delay Generator DX LED on green FPGA programmed SX LED on orange FPGA not programmed COLOR SX LED Orange DX LED Green POWER SUPPLY LEDs FUNCTION Two LEDs placed under the Gate and Delay Generator light up if the 3 3V power supply for the digital circuitry is provi...

Страница 19: ...nvert NIM OUT Direct Signal Single ended NIM TTL selectable Open 50 Ω termination selectable Bandwidth 250 MHz Front Panel Connector LEMO 00 GATE and DELAY GENERATOR Minimum Delay Gate Min Typ Max 9 6 ns 10 7 ns 11 8 ns Maximum Delay Gate 631 µs 701 2 µs 771 5 µs Maximum channel to channel spread 20 COMMUNICATION INTERFACE VME VME64X compliant Addressing space A24 A32 Data Transfer mode D16 D32 BL...

Страница 20: ...ails are not used Tab 6 4 A395C Mezzanine specifications table A395D Mezzanine Board I O SECTION Nr of Channels 8 Direction I O selectable Logic Direct Signal TTL IN Direct TTL OUT Direct NIM IN Invert NIM OUT Direct Bandwidth 250 MHz Front Panel Connector LEMO 00 POWER CONSUMPTIONS 1 1 A max 5V 12V and 12V rails are not used Tab 6 5 A395D Mezzanine specifications table A395E Mezzanine Board I O S...

Страница 21: ...ing Started with V2495 7 1 Shipping Content DESCRIPTION ITEM V2495 Programmable VME Logic Unit Without mezzanine board extension s With mezzanine board extension s according to the order USB cable V2495 User Manual Mezzanine boards are available by ordering option refer to Tab 1 2 ...

Страница 22: ... the metal cover of one of the available mezzanine slots Plug the mezzanine board into the 100 pin expansion connector on the motherboard see Chap 5 Fix the mezzanine board with the screws Fig 7 1 V2495 motherboard with mezzanine boards OPERATING THE V2495 WITH MORE THAN ONE A395C OR A395D MEZZANINE BOARDS REQUIRES USING VME CRATES WITH FORCED COOLING AIR FLOW SINCE OVERHEATING DUE TO INSUFFICIENT...

Страница 23: ...is shown in Fig 7 2 CH0 CH0 CH1 CH1 CH16 CH16 CH17 CH17 CH14 CH14 CH15 CH15 CH30 CH30 CH31 CH31 N C N C N C N C Fig 7 2 Multi pin connector pin assignment The CAEN A967 Cable Adapter Fig 7 3 allows to adapt each Robinson Nugent multi pin connector into two 1 17 17 pin Header type male connectors 3M 4634 7301 with locks through two 25 cm long flat cables Refer to the cable datasheet RD3 for specifi...

Страница 24: ... User FPGA Firmware Fig 7 5 User Firmware rotary switch The on board SW5 rotary switch selects which of the six firmware images will be loaded on the UFPGA at power on Five demos and one boot and recovery factory firmware are preloaded in the flash memory see Chap 11 for details Default SW5 position map Position 0 Factory User Firmware this copy is used as recovery boot and is not writable by the ...

Страница 25: ...may not have been configured In this case the user can take different actions according to the status of the internal configuration LEDs If the MFPGA Configuration LED is off an attempt to force the MFPGA in Factory mode can be performed see next paragraph If the CFG LED starts blinking an application firmware upgrade can be attempted If the UFPGA Configuration LED is off when the SW5 selector is ...

Страница 26: ...anel USB interface see Chap 4 the related driver can be downloaded from the V2495 webpage in the Software Firmware tab login required The USB driver is provided for Windows and Linux OS WINDOWS OS A step by step driver installation procedure is given next Note The procedure is based on a Windows 10 system It may be slightly different for another Windows OS 1 Download and unpack the driver installa...

Страница 27: ...r Manual rev 1 27 4 Right click on V2495 item and select Update Driver Software option in the slide menu Fig 8 2 USB driver manual installation Step1 5 Select Browse my computer for driver software as in Fig 8 3 Fig 8 3 USB driver manual installation Step2 ...

Страница 28: ...nual rev 1 28 6 Use the Browse button to point to the driver folder in the destination path on the host PC Fig 8 4 USB driver manual installation Step3 7 Click the Close button at the end of the installation process Fig 8 5 USB driver manual installation Step4 ...

Страница 29: ...ridge mod V2718 V1718 USB Driver The required driver can be downloaded from the V1718 web page in the Software Firmware tab login required and manually installed The installation procedure described for the direct USB driver can be taken as reference CONET Driver The V2718 requires the installation of either a PCI mod A2818 or a PCIe card mod A3818 on your PC The related drivers should be installe...

Страница 30: ...aded from the CAEN web site login required at Home Products Firmware Software Digitizer Software Configuration Tools CAENUpgrader For any installation and functions which are not described in this manual please refer to the software Quick Start Guide RD1 Get the V2495 Main FPGA Firmware Release The following instructions allow to read the release number of the MFPGA firmware 1 Select the Get Firmw...

Страница 31: ...he Board tab 2 Select the V2495 item in the Board Model combo box 3 Set the connection parameters according to your communication link and hardware setup all the parameters are detailed in RD1 4 Select the MFPGA by checking the relevant checkbox 5 Select the Main application firmware RPD file 6 Press the Upgrade button The outcome of the upgrade process is shown in a message window see Fig 8 8 7 P...

Страница 32: ...ing the relevant checkbox 5 Select the target application image on which you want to upload your firmware see Fig 8 9 Fig 8 9 CAENUpgrader UFPGA flash memory image menu 6 Select your User firmware or a CAEN Demo firmware RPD file 7 Press the Upgrade button The outcome of the upgrade process is shown in a message window see Fig 8 10 At the end of the upgrade process the CAEN Upgrader will force a r...

Страница 33: ...V2718 and V1718 if supported The library includes a simple demo application which is not intended for the board readout but rather to automatically test the library functions The user can then inspect the code as reference for his customized software development based on the PLU library Fig 8 11 CAEN PLULib Demo application prompt CAEN PLULib library can operate on Windows and Linux 32 and 64 bit ...

Страница 34: ...F The geographical address corresponds to the slot identification number of the standard VME crate 1 is the leftmost slot 21 is the rightmost slot VX2495 module inserted in slot 3 for instance could be accessed with 0x2F address modifier at base address equal to 0x180000 Registers can all be accessed via VME bus in A24 A32 addressing mode and D32 mode VME interface supports interrupt generation re...

Страница 35: ...er over the internal local bus between the MFPGA and UFPGA a data prefetch mechanism implemented in the MFPGA stores User data into a local data queue prefetch data queue Please refer to the prefetch mechanism description in Sect Local Bus Interface In consequence data from the UFPGA data access space are read from the prefetch data queue in the MFPGA User FPGA Register Access 0x1000 0x7FFF UFPGA ...

Страница 36: ...Bit Description 31 1 reserved 0 VME Interrupt Mode 0 Release On Register Access RORA Interrupt mode default 1 Release On AcKnowledge ROAK Interrupt mode VME Interrupt Level Register Bit Description 31 3 reserved 2 0 VME Interrupt Level 0 interrupts are disabled default n interrupts on IRQn line are enabled n 1 2 7 VME Interrupt Status ID Register Bit Description 31 0 This register contains the 32 ...

Страница 37: ... 0x84 constant0 0x8118 0x01 c_code 0x811C 0x43 r_code 0x8120 0x52 oui2 0x8124 0x00 oui1 0x8128 0x40 oui0 0x812C 0xE6 version 0x8130 0x00 V2495 0x01 VX2495 board2 0x8134 0x00 board1 0x8138 0x09 board0 0x813C 0xBF revis3 0x8140 0x00 revis2 0x8144 0x00 revis1 0x8148 0x00 revis0 0x814C PCB revision sernum1 0x8180 Serial Number MSB sernum0 0x8184 Serial Number LSB Tab 9 3 ROM Address Map of the V2495 N...

Страница 38: ...on 31 0 The value written into this register will determine the kind of software reset 1 generate a local bus reset only nLBRES local bus signal Others reserved for future options Scratch Register Bit Description 31 0 This register allows to perform 32 bit accesses for test purposes Default value is 0xAAAAAAAA Flash Configuration 0x8500 0x8AFF This address range is reserved to flash remote program...

Страница 39: ...s mezzanine cards The code of these demos together with a template firmware can be downloaded from the CAEN website When developing custom projects it is recommended to start with the included template firmware as it includes the correct FPGA pinning and constraints A short description of the user top level I O signals will also be given The V2495 board is an upgraded version of the V1495 board Th...

Страница 40: ...ctive low 0 output 1 input Tab 10 3 LEMO G ports description table It should be noted that the ports G0 G1 can be set as inputs in two different ways By setting nOEG 1 and driving the LEMO inputs In this way both ports will be used as inputs their status can be read from GIN 0 and GIN 1 By setting to 0 both nOEG and the output signal of the input port and enabling the related 50 Ohm termination se...

Страница 41: ...d When this mezzanine is not used these signals can be left undriven Mezzanines with 32 I O signals have a one to one correspondence between physical signals and I O pins i e X i corresponds to the i th channel of the mezzanine In case the A395D mezzanine is used the mapping between the external channels and the X bus is shown in Tab 10 5 A schematic view of the A395D board is shown in Fig 10 1 CH...

Страница 42: ...TION GD_START 32 Output GDG start signals GD_DELAYED 32 Input GDG output signals SPI_MISO 1 Input SPI MISO Master Input Slave Output SPI_SCLK 1 Output Serial clock SPI_CS 1 Output SPI Chip Select SPI_MOSI 1 Output SPI MOSI Master Output Slave Input Tab 10 7 Gate and Delay Generator ports description table Local Bus ports The Local Bus signals are shown in Tab 10 8 SIGNAL NAME WIDTH TYPE DESCRIPTIO...

Страница 43: ...dy for r w data transfer It can also be used for the data prefetch mechanism see next nBLAST OUT AL it signals the last cycle of a data transfer It is set when either the LBS is not ready or the LBM cannot accept data e g because the FIFO used for data prefetch is full LAD IN OUT the 16 bit bus used to read write both address and data LBM can generate two kind of transfers over the local bus Singl...

Страница 44: ...r request is pending and the local bus master has available space into the prefetch queue it will start an internal block transfer from local bus address 0x0000 fixed The User logic is required to respond only to address 0x0000 data from its data queue are made available to the V2495 local bus If a new register access is requested to the local bus master while a prefetch cycle is ongoing the prefe...

Страница 45: ... if Nd 0 Ttrail 0 if Nd Ng 0 T0 T1 Nd Ng 1 if Nd Ng 1 The relationship between Tlead Ttrail and the delay and gate duration is Tdelay Tlead Tgate Ttrail Tlead Fig 10 5 Gate and Delay parameters representation T1 represents the minimum increment of either the gate or the delay value The presence of T0 is due to a slightly longer duration of the minimum delay time increment or gate increment if the ...

Страница 46: ...or delay must be written here before it is transmitted through SPI to the GDG Address 0x7F00 Mode Read only Bit Description 31 0 Gate or delay datum to transmit to the GDG COMMAND register it is where the action to be performed is set The action depends on the value of the 2 LSBs of the Control register read or write mode one of these bits should be asserted to execute the related action The chann...

Страница 47: ... registers quoted are accessible via VME Set a delay gate value in the DATA WRITE register Set the COMMAND register to 0x2000 0x3000 to modify the delay gate internal value Set the control register to 0x1 0x0 Set the COMMAND register to 0x100 CHANNEL 6 bits to write the gate and delay values on the FPGA through the SPI bus for the channel specified by the six LSBs Note that the gate and delay valu...

Страница 48: ...l possible with V2495 but discouraged Register access should always be in D32 mode o Common registers with different address VME Interrupt level register 0x8004 in V1495 0x8008 in V2495 VME Interrupt Status ID register 0x8006 in V1495 0x800C in V2495 GEO address register 0x8008 in V1495 0x8010 in V2495 Firmware revision 0x800C in V1495 0x8200 in V2495 The local bus map is the same for V1495 and V2...

Страница 49: ...ser LED with the following configurations Demo Description Demo1 LED 0 ON others OFF Demo2 LED 1 ON others OFF Demo3 LED 1 and LED 0 ON others OFF Demo4 LED 2 ON others OFF 11 2 Demo Structure All demo projects feature a common file structure A configuration file V2495_package vhd allowing to set the number of CONFIG and MONITOR registers their respective base address the demo ID and the firmware ...

Страница 50: ...Base 0x1010 Base 0x1800 Base 0x1804 Base 0x1808 Base 0x180C Firmware version Value of port A input Value of port B input Value of port C output Status register Mask of input port A Mask of input port B Control register User Value of port C A24 A32 A24 A32 A24 A32 A24 A32 A24 A32 A24 A32 A24 A32 A24 A32 A24 A32 D16 D32 D16 D32 D16 D32 D16 D32 D16 D32 D16 D32 D16 D32 D16 D32 D16 D32 R R R R R R W R ...

Страница 51: ...rved 8 Allows to select the signal type on ports G0 G1 0 NIM level 1 TTL level 7 6 Reserved 5 The gate of input port C ends when this bit is set 4 The gate of input port C starts when this bit is set 3 0 0x0 the port A possibly masked is sent to C when a gate signal is active 0x1 the port B possibly masked is sent to C when a gate signal is active 0x2 the AND of A and B possibly masked is sent t t...

Страница 52: ...ion UM5175 V2495 VX2495 User Manual rev 1 52 C PORT USER VALUE register Allows to set the C port value when Control register bits 3 0 are set to 0x9 0xF Address 0x180C Mode Read and Write Bit Description 31 0 User value of Port C ...

Страница 53: ... levels NIM or TTL should be provided All registers are 32 bit wide and can be accessed in single access mode ADDRESS REGISTER CONTENT ACCESS MODE Read Write Base 0x0000 Base 0x1000 Base 0x1004 Base 0x1008 Base 0x100C Base 0x1800 Base 0x1804 Base 0x1808 Base 0x180C FIFO content readout Firmware version Value of port A input Value of port B input Value of port C output Mask of input port A Mask of ...

Страница 54: ...et to 1 means that the corresponding channel of port B is masked CONTROL register allows to set the demo configuration Address 0x1808 Mode Read and Write Bit Description 31 20 Number of stored samples in the FIFO 19 16 Downsampling factor frequency divider 15 10 reserved 9 Software acquisition start 8 Software acquisition stop 7 6 reserved 5 4 Output selection port C 00 Port A 01 Port B 10 clock c...

Страница 55: ...16 D32 R R R W R W Register Description FIRMWARE VERSION register Stores the revision number of the firmware Address 0x1000 Mode Read only Bit Description 31 0 Revision Number MEZZANINE ID NUMBER register Contains the Mezzanine ID values see Tab 10 4 Address 0x1004 Mode Read only Bit Description 31 12 reserved 11 8 Mezzanine ID port F 7 4 Mezzanine ID port E 3 0 Mezzanine ID port D CONTROL registe...

Страница 56: ...ntains the DAC value of the channel specified by bits 21 16 of the register 0x1800 Address 0x1804 Mode Read and Write Bit Description 31 0 DAC value Please note that the DAC value obtained from register 0x1804 is not read from the chip but it is the last set value for that specific channel ...

Страница 57: ...te Base 0x1000 Base 0x1800 Base 0x1804 Firmware Version Control register Clock frequency register A24 A32 A24 A32 A24 A32 D16 D32 D16 D32 D16 D32 R R W R W The registers of the Gate and Delay controller are used to configure the GDG parameters ADDRESS REGISTER CONTENT ACCESS MODE Read Write Base 0x7F00 Base 0x7F04 Base 0x7F08 Base 0x7F0C Base 0x7F10 Data write register Command register Control reg...

Страница 58: ...e gate internal buffer 0x3 The content of the Data write register is written in the delay internal buffer Control register 1 1 0x2 The gate value of the channel specified by 7 0 is read 0x3 The delay value of the channel specified by 7 0 is read 11 8 0x1 The values of gate and delay previously buffered using 15 12 are sent to the DFPGA for the channel specified by 7 0 0x3 The delays are reset 0x4 ...

Страница 59: ...ual rev 1 59 STATUS register Address 0x7F10 Mode Read only Bit Description 31 1 reserved 0 Gate and delay ready signal when 0 the Gate and Delay controller is busy A new command to the Gate and Delay controller should not be issued before this bit sets back to 1 ...

Страница 60: ...r Manual rev 1 60 12 Software Development Software applications can be developed for the V2495 by using the functions and features provided by the CAEN PLULib library RD4 CAEN PLULib library requires the Main FPGA Application Firmware revision 1 4 or higher ...

Страница 61: ...d and submitted from the Returns and Repairs area at Home Support Services with a detailed description of the specific failure A printed copy of the PRF must also be included in the package to be shipped Contacts for shipping are reported on the website at Home Contacts 13 2 Technical Support Service CAEN makes available the technical support of its specialists at the e mail addresses below suppor...

Страница 62: ... including engineers scientists and technical professionals who all trust them to help achieve their goals faster and more effectively CAEN S p A CAEN GmbH CAEN Technologies Inc Via Vetraia 11 Klingenstraße 108 1140 Bay Street Suite 2 C 55049 Viareggio D 42651 Solingen Staten Island NY 10305 Italy Germany USA Tel 39 0584 388 398 Phone 49 0 212 254 4077 Tel 1 718 981 0401 Fax 39 0584 388 959 Fax 49...

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