Caen V2495, Руководство пользователя

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CAEN
Electronic Instrumentation
UM5175 – V2495/VX2495 User Manual rev. 1
47
➢
CONTROL register: bit[0] sets a write or read action.
Address: 0x7F08.
Mode: Read only.
Bit Description
[31:2] reserved
[1] 1 = a read action is performed
[0] 1 = a write action is performed
➢
DATA READ: it is where the datum (gate or delay) can be read after an SPI read access to the GDG has been
performed (see the Read Mode of the COMMAND register).
Address: 0x7F0C.
Mode: Read only.
Bit Description
[31:0] Gate or delay datum resulting from READ MODE access to GDG
➢
STATUS register
Address: 0x7F10.
Mode: Read only.
Bit Description
[31:1] reserved
[0]
Gate and delay ready signal (when 0, the Gate and Delay controller is busy. A new command
to the Gate and Delay controller should not be issued before this bit sets back to 1)
Example Procedures
•
MODIFY THE GATE OR THE DELAY VALUE OF A CHANNEL
The gate or the delay of a signal from the UFPGA can be modified by following this procedure (the registers quoted are
accessible via VME):
- Set a delay (gate) value in the DATA WRITE register
- Set the COMMAND register to 0x2000 (0x3000) to modify the delay (gate) internal value
- Set the control register to 0x1/0x0
- Set the COMMAND register to 0x100 + CHANNEL (6 bits) to write the gate and delay values on the FPGA
through the SPI bus, for the channel specified by the six LSBs. Note that the gate and delay values are
written in the same action
- Set the CONTROL register to 0x1/0x0
•
READ THE GATE OR THE DELAY VALUE OF A CHANNEL
- Set the COMMAND register to 0x2000 (0x3000) + CHANNEL (6 bits) to read the delay (gate) value of a
specific channel
- Set the CONTROL register to 0x2/0x0
- Read the required value in the DATA READ register
•
BROADCAST A GATE OR DELAY VALUE OF A CHANNEL
- Set the desired values of the delay and gate values (see the first example, first two steps)
- Set the COMMAND register to 0x500
- Set the CONTROL register to 0x1/0x0
Note that in the case of a broadcast command the delay and gate values are serialized to the GDG at the same time.
The bits related to the channel index (six LSBs of the CONTROL register) are irrelevant in this case.