Caen V2495, Руководство пользователя

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CAEN
Electronic Instrumentation
UM5175 – V2495/VX2495 User Manual rev. 1
45
10.4 Gate and Delay Controller
General Description
The GDG can be used by the user logic to gate and delay up to 32 digital signals. The delay and gate values can be set
using a dedicated serial bus (SPI bus). The signals are sent to the GDG, where they are gated and delayed according to
the user settings and then returned to the UFPGA. The width of the delayed signal only depends on the gate value set
and is not related to the width of the incoming signal.
The gate and delay values are 16-bit wide and their sum cannot exceed 65535 (0xFFFF). They are both generated by
using an internal clock, which computes the number of clock cycles between the incoming signal and the leading and
trailing edge of the gate signal. Referring to
Fig. 10.5 , the times of occurrence of the leading (T
lead
) and trailing (T
trail
)
can be obtained using the following formulas, where N
g
(N
d
) is the gate(delay) value set by register and T
0
, T
1
are the
time values reported in Tab. 10.9 :
T
lead
= 0 if N
d
=0
T
0
+T
1
(Nd-1) if N
d
>0
T
trail
= 0 if N
d
=N
g
=0
T
0
+T
1
(N
d
+N
g
-1) if (N
d
+N
g
)≥1
The relationship between T
lead
, T
trail
and the delay and gate duration is:
T
delay
=T
lead
T
gate
=T
trail
-T
lead
Fig. 10.5: Gate and Delay parameters representation
T
1
represents the minimum increment of either the gate or the delay value. The presence of T
0
is due to a slightly
longer duration of the minimum delay time increment (or gate increment, if the N
g
=0) with respect to the standard T
1
increment. It should be noted that both T
1
and T
0
can vary from channel to channel, with an expected variation interval
of ±10% for both. Please also consider that, when setting N
d
=0, the observed delay of the outgoing signal with respect
to the incoming one is due to the paths on the PCB and inside the FPGAs, which are delay channel-dependent.
Example 1 : If the delay value is set to 0x0 and the gate value is set to 0x5, the gate will last 12.2+10.7*4=55 ns.
Example 2 : If the delay value is set to 0x8 (typ. 12+7*10.7=86.9 ns), the maximum possible gate value is 0xFFF8 (typ.
65527*10.7 ≈ 701 µ s).
Example 3 : If the delay value is set to 0xFFF8 (≈ 701 µs), the ma maximum possible gate value is 0x8 (typ. 86.9 ns).
PARAMETER VALUE
T
0
12 ns (typ.) ± 10%
T
1
10.7 ns (typ.)
±
10%
T
max
T
0
+ T
1
(2
16
-1)
Tab. 10.9: Main parameters of the Gate and Delay Generator