Caen V2495, Руководство пользователя

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CAEN
Electronic Instrumentation
UM5175 – V2495/VX2495 User Manual rev. 1
35
9.3 Address Map
The following table illustrates the V2495 address map:
Address Description
BA + 0x0000-0x0FFF UFPGA data access
BA + 0x1000-0x7FFF UFPGA register access
BA + 0x8000-0x80FF VME Interface Registers
BA + 0x8100-0x81FF Configuration ROM
BA + 0x8200-0x83FF Configuration and Status Registers
BA + 0x8400-0x84FF Reserved
BA + 0x8500-0x86FF MFPGA flash configuration
BA + 0x8700-0x88FF UFPGA flash configuration
BA + 0x8900-0x8AFF GDG flash configuration
BA + 0x8B00-x8BFF Reserved
BA + 0x8C00-0x8FFF Internal scratch RAM
BA + 0x9000-0xFFFF reserved
Tab. 9.1: V2495 register address map
User FPGA Data Access (0x0000-0x0FFF)
The UFPGA data access space is allocated specifically for the readout of data produced in the UFPGA logic which need
to exploit the maximum readout throughput available. This space can be accessed by using the available block transfer
mechanism over the VME or USB communication interfaces.
Block data transfer allows to implement a faster readout. Block transfers requests over VME or USB do not trigger any
transfer over the internal local bus between the MFPGA and UFPGA: a data prefetch mechanism, implemented in the
MFPGA, stores User data into a local data queue (prefetch data queue). Please, refer to the prefetch mechanism
description in Sect.
Local Bus Interface . In consequence, data from the UFPGA data access space are read from the
prefetch data queue in the MFPGA.
User FPGA Register Access (0x1000-0x7FFF)
UFPGA register address range is allocated for User register read/write.
A read or write transfer (single cycle) can be triggered on the local bus by performing a corresponding read transfer in
the 0x1000-0x7FFF address interval.
The local bus master in the MFPGA acts as a transparent bridge between the communication interface (VME/USB) and
the local bus in this interval. A couple of examples are given to illustrate the transparent bridge behaviour.
•
VME register access
Assume the board has a base address set to 0x32100000. An access to a user register mapped at offset 0x1000 on
the local bus can be triggered by a VME corresponding read or write cycle at address 0x32101000.
•
USB register access
Each module can be individually identified over the USB bus by its serial number. An access to a user register
mapped at offset 0x1000 on the local bus can be triggered by a USB access cycle at address 0x1000.