CAEN
Electronic Instrumentation
UM5175
–
V2495/VX2495 User Manual rev. 1
43
10.3
Local Bus Interface
The Local Bus (LB) is the communication interface between the MFPGA and the UFPGA.
It is made of a Master (LBM), implemented inside the MFPGA, and of a Slave (LBS), implemented inside the UFPGA. The
communication protocol between the LBM and the LBS is based on the following signals. In what follows OUT(IN)
means that the signal goes from the LBM(LBS) to the LBS(LBM) and AL stands for active-low:
•
nADS (OUT, AL): it is set by the LBM when a r/w operation is performed. The LBS samples the register address
from LAD when nADS is set.
•
WnR (OUT): it notifies the LBS whether the access is in write- (WnR=1) or read- (WnR=0) mode. The value of
WnR is relevant only when nADS is set.
•
nREADY (IN, AL): It is a dual purpose signal. it is set by the LBS to notify the LBM that the LBS is ready for r/w
data transfer. It can also be used for the data prefetch mechanism (see next).
•
nBLAST (OUT, AL): it signals the last cycle of a data transfer. It is set when either the LBS is not ready or the LBM
cannot accept data (e.g. because the FIFO used for data prefetch is full).
•
LAD (IN/OUT): the 16-bit bus used to read/write both address and data.
LBM can generate two kind of transfers over the local bus:
•
Single word (32-bit) read/write transfer
•
Multi word prefetch transfer
Single word transfers are initiated by the LBM for register access. It it composed by a single clock address phase and
two 16-bit data phases. A data phase is completed if the LBS asserts nREADY low. The transfer ends on the second data
phase when the LBM asserts the nBLAST signal low.
Examples of the signal logic taken using Altera
TM
. For a read and a write
access on the LBS.
Fig. 10.2:
Local bus signals at a write access (x8BADF00D is written on register x1800)
Fig. 10.3:
Local bus signal at a read access (x8BADF00D is read from register x1800)
