BK Precision 844USB, Руководство пользователя

Страница: 100 / 137

The Jam™ Standard Test and Programming Language (STAPL), JEDEC standard JESD-71,
is a standard file format for ISP (In-System Programming) purposes. Jam STAPL is a freely
licensable open standard. It supports programming or configuration of programmable devices
and testing of electronic systems, using the IEEE 1149.1 Joint Test Action Group (JTAG)
interface. Device can be programmed or verified, but Jam STAPL does not generally allow
other functions such as reading a device.
The Jam STAPL programming solution consists of two components: Jam Composer and Jam
Player.
The Jam Composer is a program, generally written by a programmable logic vendor, that
generates a Jam file (.jam) containing the user data and programming algorithm required to
program a design into a device.
The Jam Player is a program that reads the Jam file and applies vectors for programming and
testing of devices in a JTAG chain.
The devices can be programmed in ZIF socket of the programmer or in target system through
ISP connector. It is indicated by [PLCC44](Jam) or (ISP-Jam) suffix after name of selected
device in control program. Multiple devices are possible to program and test via JTAG chain:
JTAG chain (ISP-Jam)
More information on the website:
http://www.altera.com
In-System Programmability Guidelines
http://www.altera.com/literature/an/an100.pdf
Using Jam STAPL for ISP & ICR via an Embedded Processor
http://www.altera.com/literature/an/an122.pdf
Software tools:
Altera:
MAX+plus II, Quartus II, SVF2Jam utility (converts a serial vector file to a Jam file),
LAT2Jam utility (converts an ispLSI3256A JEDEC file to a Jam file);
Xilinx: Xilinx ISE Webpack or Foundation software (generates STAPL file or SVF file for use
by utility SVF2Jam);
100