BECKWITH ELECTRIC M-3425A, Инструкция

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A–43
Appendix – A
System Setpoints and Settings (Cont.'d)
IPSLogic #6 (Cont.'d)
Initiating Function Timeout:
o
21 #1
o
21 #2
o
21 #3
o
24DT #1
o
24DT #2
o
24IT
o
25D
o
25S
o
27 #1
o
27 #2
o
27 #3
o
27TN #1
o
27TN #2
o
32 #1
o
32 #2
o
32 #3
o
40 #1
o
40 #2
o
40VC #1
o
40VC #2
o
46DT
o
46IT
o
49 #1
o
49 #2
o
50 #1
o
50 #2
o
50BF
o
50DT #1
o
50DT #2
o
50N
o
50/27
o
51N
o
51V
o
59 #1
o
59 #2
o
59 #3
o
59X #1
o
59X #2
o
60FL
o
64B
o
64F #1
o
64F #2
o
64S
o
67N DT
o
67N IT
o
78
o
81 #1
o
81 #2
o
81 #3
o
81 #4
o
81A #1
o
81A #2
o
81A #3
o
81A #4
o
81A #5
o
81A #6
o
81R #1
o
81R #2
o
87 #1
o
87 #2
o
87GD
o
IPSL #1
o
IPSL #2
o
IPSL #3
o
IPSL #4
o
IPSL #5
o
IPS #6
o
BM
o
TC
Initiating Function Pickup/Timeout Logic Gate:
o
[OR]
o
AND
Initiating Function Pickup/Timeout Logic Gate:
o
[None]
o
NOT
Initiating Inputs:
o
#1
o
#2
o
#3
o
#4
o
#5
o
#6
o
#7
o
#8
o
#9
o
#10
o
#11
o
#12
o
#13
o
#14
Initiating Inputs Logic Gate:
o
[OR]
o
AND
Initiate via Communication Point:
o
Blocking Inputs:
o
FL
o
#1
o
#2
o
#3
o
#4
o
#5
o
#6
o
#7
o
#8
o
#9
o
#10
o
#11
o
#12
o
#13
o
#14
Blocking Inputs Logic Gate:
o
[OR]
o
AND
Block via Communication Point:
o
Initiating Outputs/Function Pickup/Function Timeout Logic Gate:
o
[OR]
o
AND
Initiating Outputs/Function Pickup/Function Timeout and Initiating Inputs
Logic Gate:
o
[OR]
o
AND
Delay: _____ 1 – 8160 (Cycles) [30]
Reset/Dropout Delay: _____ 0 – 65500 (Cycles) [30]
o
[Reset]
o
Dropout
Outputs:
o
#1
o
#2
o
#3
o
#4
o
#5
o
#6
o
#7
o
#8
o
#9
o
#10
o
#11
o
#12
o
#13
o
#14
o
#15
o
#16
o
#17
o
#18
o
#19
o
#20
o
#21
o
#22
o
#23
Profile Switch:
o
#1
o
#2
o
#3
o
#4
o
[Not Activated]
Reset/Dropout Delay: _____ 0 – 65500 (Cycles)
o
Reset
o
Dropout
Outputs:
o
#1
o
#2
o
#3
o
#4
o
#5
o
#6
o
#7
o
#8
o
#9
o
#10
o
#11
o
#12
o
#13
o
#14
o
#15
o
#16
Reset Latched Outputs
o
Profile Switch:
o
#1
o
#2
o
#3
o
#4
o
Not Activated
Figure A-3 System Setpoints and Settings (page 37 of 38)