Beck IPC@CHIP SC2x3, Руководство по оборудованию

Страница: 19 / 42

IPC@CHIP SC2x3
Hardware Manual V1.02 [01.03.09]
©2000-2009 BECK IPC GmbH Page 19
4.14 COP/JTAG-Interface
Pin Name Pin Con Type Description
JTAG_TCK
14 X3
IN
JTAG Clock (Schmitt Trigger Input with internal 10kOhm
pullup)
The (non-reset) behavior of the active TAP and TLM state
machines is governed by the TMS value at the TCK rising
edge. TDI value is sampled at the TCK rising edge for all
shift operations. All TDO non-reset transitions (including
impedance) occur at the TCK falling edge. All shift register
capture operations occur at the TCK rising edge. All shift
register Update operations occur at the TCK falling edge.
JTAG_TDI
9 X3
IN JTAG Data Input (with internal 10kOhm pullup)
Serial test data input can be routed to any IR or DR, as
determined by the state of the active TAP state machine and
the contents of the active IR. TDI is sampled at the TCK
rising edge while the active TAP state machine is in either
the Shift-IR or Shift-DR state.
JTAG_TDO
8 X3
OUT [8mA] JTAG Data Output
TDO when connected to TDI (of another device), TDO
switches at the TCK falling edge. TDO is driven while the
TLM state machine is in the Shift-IR or Shift-DR states only;
it is tri-stated in all other TAP
states. Except, for the first half clock after exiting the shift
state, because of its falling edge timing.
JTAG_TMS
7 X3
IN JTAG Mode Select (with internal 10kOhm pullup)
TAP state machine control, including TLM. The state of TMS
at rising edges of TCK uniquely determines the state
sequence of the TLM and the active TAP state machines.
Inactive TAPs ignore TMS completely.
JTAG_TRST#
11 X3
IN
JTAG Reset (Active Low with internal Pull-up)
When asserted, any on-going JTAG operation is immediately
aborted. All TAP state machines, including the TLM,
immediately enter the Test-Logic-Reset state. Other JTAG
input signals (TCK, TMS, and TDI) have no effect while
TRST is asserted. TDO is immediately tri-stated.
TEST_SEL_0 16 X3 IN
TEST_SEL_1 12 X3 IN internal 10kOhm pullup
Table 4-12: Pin Description of COP/JTAG-Interface
4.15 Interrupts
Pin Name Pin Con Type Description
IRQ0 30 X1 IN Interrupt 0 (Active High with internal 100kOhm pullup)
This pin is the external interrupt 0 request.
IRQ1 27 X1 IN Interrupt 1 (Active High with internal 100kOhm pullup)
This pin is the external interrupt 0 request.
IRQ2 28 X1 IN Interrupt 2 (Active High with internal 100kOhm pulldown)
This pin is the external interrupt 0 request.
IRQ3 23 X1 IN Interrupt 3 (Active High with internal 100kOhm pulldown)
This pin is the external interrupt 0 request.
Table 4-13: Pin Description of Interrupts