Artesyn Embedded Technology ATCA-7540, Инструкция по установке и эксплуатации, Страница: 166 / 324

Maps and Registers
166 ATCA-7540 Installation and Use (6806871A01A )
7
Measurement Mode:
0: Gate Mode. Count positive clock edges during open gate.
1: Period Mode. Count number of clocks which fit in one period.
0 LPC: r/w
Table 5-96. Telecom Clock Monitor Frequency/Period Register
Address: 0x65-0x66
Bit
Description Default Access
15:0
Result of supervised Telecom Clock.
Gate mode:
0: No clock edge sampled. Clock to slow for time base
1 - 65534: Number of sampled clocks during timer base
65535: Overflow. Clock to fast for time base.
Period Mode
0: No clock edge sampled. Clock to fast for time base
1 - 65534: Number of clocks during one supervised clock
period.
65535: Overflow. Supervised clock to slow for time base.
Note: Only valid when corresponding bit in
Table 5-92
Telecom Clock Monitor Status Register is set.
0 LPC: r
Table 5-97. Telecom Clock Monitor Lower Limit Register
Address: 0x67 -0x68
Bit
Description Default Access
15:0
Lower Limit for supervised Telecom Clock:
Used by
Table 5-93
Telecom Clock Monitor Out of Range
Register
0 LPC: r/w
Table 5-98. Telecom Clock Monitor Upper Limit Register
Address: 0x69 -0x6A
Bit Description Default Access
15:0
Upper Limit for supervised Telecom Clock:
Used by
Table 5-93
Telecom Clock Monitor Out of Range
Register
0xFFFF LPC: r/w
Table 5-95. Telecom Clock Monitor Time Base Register (continued)
Address: 0x64
Bit Description Default Access