Artesyn Embedded Technology ATCA-7540, Инструкция по установке и эксплуатации, Страница: 164 / 324

Maps and Registers
164 ATCA-7540 Installation and Use (6806871A01A )
When at least one bit shown in Table 5-93 is set, the corresponding status bit
CLK_MONITOR_OUT_OF_RANGE shown in Table 5-70 is also set.
Table 5-93. Telecom Clock Monitor Out of Range Register
Address: 0x62
Bit Description Default Access
3:0
Frequency of supervised Telecom Clock 0 to 3 is out of
range.
Gate Mode:
Corresponding bit is set when the number of positive
Clock edges within the selected time base is:
< Lower limit or
> Upper limit
Period Mode:
Corresponding bit is set when the Clock 0 Period within
the selected time base is:
< Lower limit or
> Upper limit
Clearing bit triggers new sequence of measurements.
0 LPC: r/w1c
7:4 Reserved 0 r
Table 5-94. Telecom Clock Monitor Select Register
Address: 0x63
Bit Description Default Access
1:0
Select supervised Telecom Clocks. See
Table 5-90
Supervised Telecom Clocks Reference List:
0-3: Select corresponding clock
0 LPC: r/w
7:2 Reserved 0 r