Artesyn Embedded Technology ATCA-7540, Инструкция по установке и эксплуатации, Страница: 96 / 324

Functional Description
96 ATCA-7540 Installation and Use (6806871A01A )
4.19 System Clocks
The ATCA-7540 blade provides the system clocks using the PCH operating in a hybrid clock
mode. Most of the clocks are provided directly by the PCH. A 9ZXL0651 clock buffer or
equivalent is added to provide the 100 MHz PCIe clocks to some of the PCIe devices. Various
crystals and crystal oscillators are also used. The PCH CLKOUT_SRC pins have associated
output enable pins which are controlled by the IPMC (for RTM clocks) and the FPGA (for CPU
clocks).
4.20 SMBus
The PCH provides an SMBus host controller/slave interface along with six SMLink interfaces,
SMLink0B and SMLink0-4. These interfaces are intended for system management and are
controlled by the Management Engine (ME). SMLink1 is connected to the VR13 power
controllers. SMLink0 and SMLink2 are connected to IPMB buses L2 and L3.
Only four interfaces are used on ATCA-7540 as described in the following table.
The Master SMBus interface of the Lewisburg PCH is connected to on-board devices like Clock
PLLs, temperature sensors, and so on.
Additionally, both CPUs provide 2x SMBus to connect to the SPD PROMs of the DDR4 memory
system.
The following figure shows the ATCA-7540 SMBus architecture.
Table 4-4. SMBus Interface
Device / SMBus Description
SMBus Host SMBus (Master/Slave)
SMLink0
Connection to external IPMC to report thermal information via PCH
internal PECI
bridge to CPU
SMLink1 VR13 power controllers
SMLink 2 IPMB-L2