Artesyn Embedded Technology ATCA-7540, Инструкция по установке и эксплуатации, Страница: 125 / 324

Maps and Registers
ATCA-7540 Installation and Use (6806871A01A) 125
A divisor value of 0 in the Divisor Latch Register is not allowed.
5.1.5 FPGA Register Mapping
5.1.5.1 LPC I/O Register Map
The FPGA registers can be accessed via LPC I/O cycles in the I/O address range REGISTERS. See
Table 5-38 FPGA Register Map Overview. For a LPC register access the host uses the base
address, 0x600. Individual registers can be accessed by adding an offset to the base address.
An LPC I/O write access to an address not listed in this table or marked with an “-” in the LPC I/O
column is ignored. A corresponding read access delivers always zero — used and reserved for
future extensions. A reserved register is read only and deliver always zero. A reserved bit is read-
only and always reads zero.
Table 5-36. Divisor Latch LSB Register (DLL), if DLAB=1
PC I/O Address: Base
Bit Description Default Access
7:0 Divisor Latch LSB (DLL) Undef. LPC: r/w
Table 5-37. Divisor Latch MSB Register (DLM), if DLAB=1
LPC I/O Address: Base + 1
Bit Description Default Access
7:0 Divisor Latch MSB (DLM) Undef. LPC: r/w
NOTICE
LPC I/O Address = 0x600 + Address Offset