Anritsu MT9812B, Руководство по эксплуатации, Страница: 96 / 144

Section 5 Remote Control
5-28
5.5.3 Reading and Clearing the Status Byte Register
Status byte register contents can be read using serial polling or an
∗
STB? com-
mon inquiry. IEEE 488.1 defined STB messages can be read by either method,
but the value transferred to bit 6 (position) varies depending on the method.
status byte register contents can be cleared using a
∗
CLS command.
(1) Reading the status byte register using serial polling (only when
a GPIB interface bus is used)
When IEEE 488.1 defined serial polling is carried out, the device must re-
turn a 7 bit status byte and IEEE 488.1 defined RQS message bit. According
to IEEE 488.1, the RQS message indicates whether the device has issued
SRQs in the True state. The status byte value is not affected by serial poll-
ing. Immediately after being polled, the device must set the rsv message in
the False state. If the device is polled again before a cause of issuing a new
service request occurs, the RQS message has already been set in the False
state.
(2) Reading the status byte register using an
∗
STB? common query
The
∗
STB? common query causes the device to output status byte register
contents and one <NR1 NUMERIC RESPONSE DATA> from the MSS
summary message. The response is the total of the status register value
assigned binary weights and MSS summary message value. Status byte
register bits 0 to 5 and 7 are assigned weighs 1, 2, 4, 8, 16, 32, and 128
respectively, and the MSS is assigned weights 64. The response to the
∗
STB? is the same as that to serial polling with the exception that an MSS
summary message appears in bit 6 instead of an RQS message.
(3) Definition of MSS (Master Summary Status)
The MSS indicates that the device has at least one cause of issuing a service
request. In the device's response to the
∗
STB? query, the MSS message
appears in bit 6. However, it does not appear in the response to serial poll-
ing. It must not be regarded as part of the IEEE 488.1 defined status byte.
The MSS is the result of ORing the values of status byte register and SRQ
enable (SRE) register bits totally. Specifically, the MSS is defined as fol-
lows:
(STB Register bit 0 AND SRE Register bit 0)
OR
(STB Register bit 1 AND SRE Register bit 1)
OR
:
:
(STB Register bit 5 AND SRE Register bit 5)
OR
(STB Register bit 7 AND SRE Register bit 7)
In the definition of the MSS, the values of bits 6 of the status byte register
and SRQ enable register are ignored. Accordingly, when calculating the
MSS value, the status byte may be handled assuming that it is represented
by 8 bits and bit 6 is always 0.