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New iStar ICCD
Section Title
Pre-Acquisition Setup - CCD
5.3.4 - CCD Clocking speed
5.3.4.1 - Vertical Pixel shift
Shift speed
Shift Speed (µsecs) specifies the time taken clock (shift) charges from one row on the CCD sensor to the next. Speeds
which appear un-bracketed in the drop-down list are guaranteed to meet all the system specifications. In some
instances, using a slightly slower vertical shift speed may result in a slight increase in the single well capacity for imaging
applications. However it may also reduce the maximum frame/spectral rates achievable.
Bracketed vertical shift speed values are also available (CCD-model dependant) to achieve even faster acquisition rates.
However, with this setting the pixel well depth and charge transfer efficiency may be impacted.
Vertical Clock Amplitude Voltage
The vertical clock voltage amplitude can be used to increase the amplitude of the clock pulses used to perform row
shifts on the CCD. The normal setting is the default amplitude which has been set at the factory during the optimization
and testing of the camera. The other settings (if available) specify the voltage increase to be applied to this clock
amplitude. In some imaging applications, increasing this voltage can provide a slightly higher single pixel well depth and
improve charge transfer efficiency, at the expense of slightly higher CIC.
Application of higher voltage may be required in combination with the fastest of the bracketed vertical pixel shift speeds
in order to overcome image distortion effects that result from reduced charge transfer efficiency. Best practice is to
select the fastest vertical shift speed, then step the vertical clock voltage 1 unit at a time until distortive effects disappear
from the image.
