ADSP-BF561 EZ-KIT Lite Evaluation System Manual
1-7
Using EZ-KIT Lite
The 8 MB of flash memory is organized as 4M x 16 bit and mapped into a
ADSP-BF561 processor’s ASYNC Memory Bank 0 (
~AMS0
, memory select
signal connects to the flash memory’s output enable pin).
The 64 MB of SDRAM is organized as 16M x 32 bits wide. The proces-
sor’s memory select pin
~SMS0
is configured for the SDRAM. Three
SDRAM control registers must be initialized in order to access the
SDRAM memory.
When in a Vi+ EZ-KIT Lite session, you can automatically con-
figure the SDRAM registers by selecting the
Use XML reset values
box on
the
Target Options
dialog box, which is accessible through the
Settings
Figure 1-2. ADSP-BF561 Processor Internal Memory Map
L1 SCRATCHPAD SRAM (4K)
L1 INSTRUCTION SRAM/CACHE (16K)
L1 INSTRUCTION SRAM (16K)
L1 DATA BANK B SRAM/CACHE (16K)
L1 DATA BANK B SRAM (16K)
L1 DATA BANK A SRAM/CACHE (16K)
L1 DATA BANK A SRAM (16K)
CORE A MEMORY MAP
CORE B MEMORY MAP
CORE MMR REGISTERS
CORE MMR REGISTERS
SYSTEM MMR REGISTERS
L1 SCRATCHPAD SRAM (4K)
RESERVED
L1 INSTRUCTION SRAM/CACHE (16K)
L1 INSTRUCTION SRAM (16K)
L1 DATA BANK B SRAM/CACHE (16K)
L1 DATA BANK B SRAM (16K)
L1 DATA BANK A SRAM/CACHE (16K)
L1 DATA BANK A SRAM (16K)
L2 SRAM (128K)
0XFFE0 0000
0XFFC0 0000
0XFFB0 1000
0XFFB0 0000
0XFFA1 4000
0XFFA1 0000
0XFFA0 4000
0XFFA0 0000
0XFF90 8000
0XFF90 4000
0XFF90 0000
0XFF80 8000
0XFF80 4000
0XFF80 0000
0XFF70 1000
0XFF70 0000
0XFF61 4000
0XFF50 4000
0XFF50 0000
0XFF40 8000
0XFF40 4000
0XFF40 0000
0XFEB2 0000
0XFEB0 0000
0XEF00 0800
0XFF61 0000
0XFF60 4000
0XFF60 0000
0XFF50 8000
0XFFFF FFFF
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Содержание ADSP-BF561 EZ-KIT Lite
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