System Architecture
2-8
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Video Input (PPI0)
The
PPI0
interface is configured as input and connect to the on-board
video decoder device, ADV7183A. The ADV7183A decoder receives three
analog video channels on
AIN1
,
AIN4
, and
AIN5
input. The decoder’s pixel
data outputs
P15
–
8
drive the
PPI0
inputs
8–0
. The decoder’s 27 MHz pixel
clock output can be selected to drive any of the PPI clocks, as shown in
Synchronization outputs of the decoder,
HS/HACTIVE
,
VS/VACTIVE
, and
FIELD
can connect to the processor’s
PPI1
SYNC1
,
SYNC2
, and
PF3
flag via
the
SW2
DIP switch, as described in
“Video Configuration Switch (SW2)”
UART Port
The processor’s Universal Asynchronous Receiver/Transmitter (UART)
port connects to the ADM3202 RS232 line driver as well as to the expan-
sion interface. The RS232 line driver is attached to the
DB9
male
connector, allowing you to interface with a PC or other serial device.
Expansion Interface
The expansion interface consists of the three 90-pin connectors,
J3–1
.
shows the interfaces each connector provides. For the exact
pinout of these connectors, refer to
Appendix B, “Schematics” on page
. The mechanical dimensions of the connectors can be obtained from
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