System Architecture
2-6
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
PPI Interfaces
The ADSP-BF561 processor employs two independent Parallel Peripheral
Interfaces (PPIs),
PPI0
and
PPI1
. Each PPI interface is a half-duplex,
bi-directional bus consisting of 16 bits of data, a dedicated input clock,
and synchronization signals. The ADSP-BF561 EZ-KIT Lite board uti-
lizes the PPI interfaces for video input and video output.
The
PPI0
interface is configured to input video data from the ADV7183A
video decoder device: bits
7–0
connect to the video decoder’s data outputs.
The
PPI1
interface is configured to output video data to the ADV7179
video encoder device: bits
7–0
connect to the video encoder’s data inputs.
Each PPI interface has a dedicated clock input configured independently
by the
SW5
switch. The clock source can be one of the following: 27 MHz
crystal oscillator, ADV7183A video decoder’s clock output, or external
clock from the expansion interface. See
“PPI Clock Select Switch (SW5)”
for more information about the switch.
The
SW2
switch allows flexible connectivity between dedicated synchroni-
zation IOs (
SYNC1
and
SYNC2
of each PPI interface) and the encoder’s and
decoder’s horizontal and vertical synchronization pins. See
figuration Switch (SW2)” on page 2-10
for more information about the
switch. For a detailed description of the ADSP-BF561 processor’s PPI
interfaces, refer to the
ADSP-BF561 Blackfin Processor Hardware Reference
.
describes the PPI pins and their use on the EZ-KIT Lite board.
Table 2-2. PPI Connections
Processor PPI
Pin
Other PRocessor
Function
EZ-KIT Function
PPI0
bits
7–0
ADV7183A data outputs
P15–8
PPI1
bits
7–0
ADV7179 data inputs
P7–0
PPI0
SYNC1
Timer 8
ADV7179
HSYNC
. For more information, see
Содержание ADSP-BF561 EZ-KIT Lite
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