External Memory
1-8
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
pull-down menu. The values for the
EBIU_SDGCTL
,
EBIU_SDBCTL
, and
EBIU_SDRRC
registers have been set in the
ADSP-BF561.xml
file found in
your
VisualDSP\SYSTEM
folder under the
RegReset
tag. These values can
be changed to be more optimal depending on the SCLK frequency.
The values in
are programmed by default whenever Bank 0 is
accessed through the debugger (for example, when viewing memory win-
dows or loading a program). The numbers are derived for maximum
flexibility and work for a system clock frequency between 60 MHz and
133 MHz.
The
EBIU_SDGCTL
register can only be written once after the processor
comes out of reset. Therefore, the user code should not reinitialize this
register. Clearing the
Use XML reset values
checkbox allows manual con-
figuration of the
EBIU
registers. For more information, see
.
Automatic configuration of the SDRAM is not optimized for a specific
SCLK frequency.
shows the optimized configuration for the
SDRAM registers using a 120 MHz SCLK. The frequency of 120 MHz is
the maximum SCLK frequency when using a 600 MHz core frequency,
the maximum frequency for the EZ-KIT Lite. Only the
SDRRC
register
needs to be modified in the user code to achieve maximum performance.
Table 1-2. EZ-KIT Lite Session SDRAM Default Settings
Register
Value
Function
EBIU_SDGCTL
0x0091998D
Calculated with SCLK = 133 MHz
EBIU_SDBCTL
0x00000013
EBIU_SDRRC
0x000001CF
Calculated with SCLK = 120 MHz
Содержание ADSP-BF561 EZ-KIT Lite
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