ADSP-BF561 EZ-KIT Lite Evaluation System Manual
2-9
EZ-KIT Lite Hardware Reference
Limits to the current and to the interface speed must be taken into consid-
eration when you use the expansion interface. The maximum current limit
is dependent on the capabilities of the used regulator. Additional circuitry
can also add extra loading to signals, decreasing their maximum effective
speed.
[
Analog Devices does not support and is not responsible for the
effects of additional circuitry.
JTAG Emulation Port
The JTAG emulation port allows an emulator to access the processor’s
internal and external memory through a 6-pin interface. The JTAG emu-
lation port of the processor also connects to the USB debugging interface.
When an emulator connects to the board at
P4
, the USB debugging inter-
face is disabled. See
about the JTAG connector.
To learn more about available emulators, contact Analog Devices (see
).
Table 2-3. Connector Interfaces
Connector Interfaces
J1
5V, G ND, Address, Data,
PPI0
3–0
,
PF15–6
,
PF4
J2
3.3V, GND, SPI, NMI,
PPI0
SYNC3–1
,
SPORT0
,
SPORT1
,
PF15–0
, EBUI control
signals
J3
5V, 3.3V, GND, UART,
PPI1
15–0
, Reset, Video control signals
Содержание ADSP-BF561 EZ-KIT Lite
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