AD9854
Rev. E | Page 27 of 52
HOLD
F1
0
FR
E
Q
U
E
N
C
Y
MODE
TW1
DFW
000 (DEFAULT)
0
RAMP RATE
011 (CHIRP)
F1
DELTA FREQUENCY WORD
RAMP RATE
I/O UD CLK
00
63
6-
04
7
Figure 47. Example of Hold Function
BPSK DATA
360
0
PH
A
SE
MODE
FTW1
PHASE ADJUST 1
000 (DEFAULT)
0
PHASE ADJUST 2
100 (BPSK)
F1
270°
90°
I/O UD CLK
00
63
6-
0
48
Figure 48. BPSK Mode
The 32-bit automatic I/O update counter can be used to
construct complex chirp or ramped FSK sequences. Because
this internal counter is synchronized with the AD9854 system
clock, precisely timed program changes are possible. For such
changes, the user need only reprogram the desired registers
before the automatic I/O update clock is generated.
In chirp mode, the destination frequency is not directly specified.
If the user fails to control the chirp, the DDS automatically confines
itself to the frequency range between dc and Nyquist. Unless
terminated by the user, the chirp continues until power is removed.
When the chirp destination frequency is reached, the user can
choose any of the following actions:
•
Stop at the destination frequency by using the HOLD pin
or by loading all 0s into the delta frequency word registers
of the frequency accumulator (ACC1).
•
Use the HOLD pin function to stop the chirp, and then ramp
down the output amplitude by using the digital multiplier
stages and the output shaped keying pin (Pin 30), or by using
the program register control (Address 21 to Address 24 hex).
•
Abruptly end the transmission with the CLR ACC2 bit.
•
Continue chirp by reversing direction and returning to
the previous or another destination frequency in a linear or
user-directed manner. If this involves reducing the
frequency, a negative 48-bit delta frequency word (the
MSB is set to 1) must be loaded into Register 10 hex to
Register 15 hex. Any decreasing frequency step of the delta
frequency word requires the MSB to be set to logic high.
