AD9854
Rev. E | Page 22 of 52
Frequency ramping, whether linear or nonlinear, necessitates
that many intermediate frequencies between F1 and F2 are
output in addition to the primary F1 and F2 frequencies.
Figure 37 and Figure 38 depict the frequency vs. time
characteristics of a linear ramped FSK signal.
Note that in ramped FSK mode, the delta frequency word (DFW)
is required to be programmed as a positive twos complement
value. Another requirement is that the lowest frequency (F1)
be programmed in the Frequency Tuning Word 1 register.
The purpose of ramped FSK is to provide better bandwidth
containment than traditional FSK by replacing the instantaneous
frequency changes with more gradual, user-defined frequency
changes. The dwell time at F1 and F2 can be equal to or much
greater than the time spent at each intermediate frequency. The
user controls the dwell time at F1 and F2, the number of inter-
mediate frequencies, and the time spent at each frequency. Unlike
unramped FSK, ramped FSK requires the lowest frequency to be
loaded into F1 registers and the highest frequency to be loaded
into F2 registers.
Several registers must be programmed to instruct the DDS on
the resolution of intermediate frequency steps (48 bits) and the
time spent at each step (20 bits). Furthermore, the CLR ACC1 bit
in the control register should be toggled (low-high-low) prior to
operation to ensure that the frequency accumulator is starting
from an all 0s output condition. For piecewise, nonlinear frequency
transitions, it is necessary to reprogram the registers while the
frequency transition is in progress to affect the desired response.
Parallel Register Address 1A hex to Parallel Register Address 1C hex
comprise the 20-bit ramp rate clock registers. This is a countdown
counter that outputs a single pulse whenever the count reaches
0. The counter is activated when a logic level change occurs on
the FSK input, Pin 29. This counter is run at the system clock
rate, 300 MHz maximum. The time period between each output
pulse is given as
(
N
+ 1) ×
System Clock Period
where
N
is the 20-bit ramp rate clock value programmed by
the user.
The allowable range of N is from 1 to (2
20
− 1). The output of
this counter clocks the 48-bit frequency accumulator shown in
Figure 39. The ramp rate clock determines the amount of time
spent at each intermediate frequency between F1 and F2. The
counter stops automatically when the destination frequency is
achieved. The dwell time spent at F1 and F2 is determined by
the duration that the FSK input, Pin 29, is held high or low after
the destination frequency has been reached.
FREQUENCY
TUNING
WORD 2
FREQUENCY
TUNING
WORD 1
20-BIT
RAMP RATE
CLOCK
48-BIT DELTA
FREQUENCY
WORD (TWOS
COMPLEMENT)
FREQUENCY
ACCUMULATOR
PHASE
ACCUMULATOR
INSTANTANEOUS
PHASE OUT
ADDER
FSK (PIN 29)
SYSTEM
CLOCK
0063
6-
039
Figure 39. Block Diagram of Ramped FSK Function
Parallel Register Address 10 hex to Parallel Register Address 15 hex
comprise the 48-bit, twos complement, delta frequency word
registers. This 48-bit word is accumulated (added to the
accumulator’s output) every time it receives a clock pulse from
the ramp rate counter. The output of this accumulator is added to
or subtracted from the F1 or F2 frequency word, which is then
fed into the input of the 48-bit phase accumulator that forms
the numerical phase steps for the sine and cosine wave outputs.
In this fashion, the output frequency is ramped up and down in
frequency according to the logic state of Pin 29. This ramping
rate is a function of the 20-bit ramp rate clock. When the
destination frequency is achieved, the ramp rate clock is
stopped, halting the frequency accumulation process.
Generally speaking, the delta frequency word is a much smaller
value compared with the value of the F1 or F2 tuning word. For
example, if F1 and F2 are 1 kHz apart at 13 MHz, the delta
frequency word might be only 25 Hz.
