AD9854
Rev. E | Page 44 of 52
output current from 10 mA to 20 mA and doubles the peak-to-
peak output voltage developed across the loads, thus resulting
in more robust signals at the comparator inputs.
Single-Ended Configuration
To connect the high speed comparator in a single-ended
configuration so that the duty cycle or pulse width can be
controlled, a dc threshold voltage must be present at one of the
comparator inputs. The user can supply this voltage using the
control DAC. A 12-bit, twos complement value is written to the
control DAC register that sets the IOUT2 output to a static dc
level. Allowable hexadecimal values are 7FF (maximum) to 800
(minimum), with all 0s being midscale. The IOUT1 channel
continues to output a filtered sine wave programmed by the
user. These two signals are routed to the comparator by using
the 3-pin W2 and W8 header switches. Use of the configuration
described in the Observing the Filtered IOUT1 and the Filtered
IOUT2 section is required. Follow Step 1 through Step 4 in this
section, and then install a shorting jumper on Pin 1 and Pin 2
(top two pins) of the 3-pin W2 and W8 headers.
The user can change the value of R
SET
Resistor R2 from 3.9 kΩ
to 1.95 kΩ to receive more robust signals at the comparator
inputs. This decreases jitter and extends the operating range of
the comparator. To implement this change install a shorting
jumper at W6, which provides a second 3.9 kΩ chip resistor
(R20) in parallel with that provided by R2.
USING THE PROVIDED SOFTWARE
The evaluation software is provided on a CD, along with a brief
set of instructions. Use the instructions in conjunction with the
AD9852 or AD9854 data sheet and the AD9852 or AD9854
evaluation board schematic.
The CD contains the following:
•
The AD9852/AD9854 evaluation software
•
AD9854 evaluation board instructions
•
AD9854 data sheet
•
AD9854 evaluation board schematics
•
AD9854 PCB layout
Several numerical entries, such as frequency and phase infor-
mation, require pressing
Enter
to register the information. For
example, if a new frequency is input but does not take effect
when
Load
is clicked, the user probably neglected to press
Enter
after typing the new frequency information.
Normal operation of the AD9852/AD9854 evaluation board
begins with a master reset. After this reset, many of the default
register values are depicted in the software control panel. The reset
command sets the DDS output amplitude to minimum and 0 Hz,
zero phase offset, as well as other states that are listed in the
Register Layout table (Table 8 for AD9854).
The next programming block should be the reference clock and
multiplier because this information is used to determine the
proper 48-bit frequency tuning words that are entered and later
calculated.
The output amplitude defaults to the 12-bit, straight binary
multiplier values of the I (cosine DAC) multiplier register of
000 hex; no output (dc) should be seen from the DAC. Set the
multiplier amplitude in the
Output Amplitude
dialog box to a
substantial value, such as FFF hex. The digital multiplier can be
bypassed by selecting
Output Amplitude is always Full Scale,
but
this usually does not result in the best spurious-free dynamic range
(SFDR). The best SFDR, achieving improvements of up to 11 dB, is
obtained by routing the signal through the digital multiplier and
then reducing the multiplier amplitude. For instance, FC0 hex
produces less spurious signal amplitude than FFF hex. If SFDR
must be maximized, this exploitable and repeatable phenomenon
should be investigated in the given application. This phenomenon
is more readily observed at higher output frequencies, where
good SFDR becomes more difficult to achieve.
Refer to this data sheet and the evaluation board schematic to
understand the available functions of the AD9854 and how the
software responds to programming commands.
SUPPORT
Applications assistance is available for the AD9854, the AD9854
PCB evaluation board, and all other Analog Devices products.
Call 1-800-ANALOGD or visit www.analog.com/dds.
