AD9854
Rev. E | Page 34 of 52
PARALLEL I/O OPERATION
With the S/P SELECT pin tied high, the parallel I/O mode is active.
The I/O port is compatible with industry-standard DSPs and
microcontrollers. Six address bits, eight bidirectional data bits,
and separate write/read control inputs comprise the I/O port pins.
Parallel I/O operation allows write access to each byte of any
register in a single I/O operation of up to one per 10.5 ns.
Readback capability for each register is included to ease designing
with the AD9854. (Reads are not guaranteed at 100 MHz because
they are intended for software debugging only.)
Parallel I/O operation timing diagrams are shown in Figure 52
and Figure 53.
SERIAL PORT I/O OPERATION
With the S/P SELECT pin tied low, the serial I/O mode is active.
The serial port is a flexible, synchronous, serial communication
port, allowing easy interface to many industry-standard micro-
controllers and microprocessors. The serial I/O is compatible
with most synchronous transfer formats, including both the
Motorola® 6905/11 SPI and Intel® 8051 SSR protocols. The
interface allows read/write access to all 12 registers that configure
the AD9854 and can be configured as a single-pin I/O (SDIO) or
two unidirectional pins for input and output (SDIO/SDO). Data
transfers are supported in MSB-or the LSB-first format for up
to 10 MHz.
When configured for serial I/O operation, most AD9854 parallel
port pins are inactive; only some pins are used for the serial I/O
operation. Table 9 describes pin requirements for serial I/O
operation.
Note that when operating the device in serial I/O mode, it
is best to use the external I/O update clock mode to avoid an
update occurring during a serial communication cycle. Such an
occurrence may cause incorrect programming due to a partial
data transfer. To exit the default internal update mode, program
the device for external update operation at power-up before
starting the REFCLK signal but after a master reset. Starting the
REFCLK causes this information to transfer to the register bank,
forcing the device to switch to external update mode.
Table 9. Serial I/O Pin Requirements
Pin Number
Mnemonic
Serial I/O
Description
1 to 8
D [7:0]
The parallel data pins are not active; tie to VDD or GND.
14 to 16
A [5:3]
The A5, A4, and A3 parallel address pins are not active; tie these pins to VDD or GND.
17
A2/IO RESET
IO RESET.
18 A1/SDO
SDO.
19 A0/SDIO
SDIO.
20
I/O UD CLK
Update Clock. Same functionality for serial mode as parallel mode.
21
WR/SCLK
SCLK.
22
RD/CS
CS—Chip Select.
