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AD9361 Reference Manual

UG-570

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SETTLING TIMES

After a gain change, the

AD9361

must reset overload detectors

and power measurement circuits and wait for the receive path to
settle before re-enabling detectors and power measurement
blocks.

PEAK OVERLOAD WAIT TIME

All gain control modes use peak overload wait time. After a gain
change, the

AD9361

waits for the time set by this register before

re-enabling its LMT and ADC overload detectors, which allows
the signal in the analog path and the ADCs to settle. The default
is fine for all applications unless an external LNA with a bypass
mode is part of the signal path. The Peak Overload Wait Time is
set by the ad9361_set_rx_gain_control_mode function and is
clocked at the ClkRF rate (the input to the Rx FIR Filter clock
rate).

SETTLING DELAY

All AGC modes use settling delay, which is the time that the AGC
holds the power measurement blocks in reset after a gain change.
Power measurement occurs at the output of the receive HB1 filter
(which is the input to the receive FIR filter) so all stages up to the
Rx FIR must have settled before power measurement resumes
after a gain change. The delay is equal to the register value
multiplied by 2 and is clocked at the ClkRF rate. The default for
settling delay is 20 ClkRF cycles, and that is based on a ClkRF rate
of 30.72 MHz. For optimum fast attack AGC performance, the
delay needs to scale with ClkRF.

GAIN TABLE OVERVIEW

The

AD9361

uses a pointer to a row in a gain table. That row

contains the gain values of each independent gain block. In this
way, a gain index value (pointer) maps to a set of gain values for
each gain block. However, there are two different ways that the

AD9361

can implement the gain table. In full table mode, there is

one table for the receiver. In split table mode, the

AD9361

splits

the LMT and LPF tables apart and controls each independently
with separate pointers. If digital gain is enabled, there is a third
table that is independently controlled, also with its own pointer.
Each receiver has its own set of two (or three) tables. The gain
table mode is set in the ad9361_load_gt function. The table
architecture affects all gain control modes and is a common
setting for both receivers.

FULL TABLE MODE

Full table mode is useful for most situations. A single gain table
contains all of the variable gain blocks in the Rx signal path.
Figure 21 shows a portion of a full gain table. The figure also
shows the gain of each block next to each gain index. If the gain
index moves up or down, the gain indices of one or more blocks
will change. If the gain index pointer moves down one step (to a
table index of 54), both the LNA gain and the LPF gain will
change. These changes allow the

AD9361

to handle widely

varying signal levels while still optimizing noise figure and
linearity.

To read back the full table gain index in any gain control mode,
read use the ad9361_get_rx_rf_gain function.

The Max LMT/Full Gain register limits the maximum index
allowed.

Figure 21. Portion of the Analog Devices 2300 MHz Example Full Gain Table

Figure 22. Split Table in Manual Gain Mode, SPI Writes Control Gain Indices

LNA

INDEX