AD9361 Reference Manual
UG-570
| Page 103 of 128
DUAL PORT FULL DUPLEX MODE (CMOS)
Dual port full duplex mode (full port) is used in applications
requiring FDD operation and data rates less than 61.44 MHz. In
this mode, both data ports are utilized, with P0 assigned to
receive data and P1 assigned to transmit data. Each bus operates
simultaneously, allowing full duplex transfer of Tx and Rx data
between the BBP and the
AD9361
. For this mode, each data bus
must operate at twice the speed of the dual port TDD mode to
achieve the same Tx and Rx data rates (as each are running
concurrently in full duplex). Each bus can be operated as either
SDR or DDR in this configuration. This mode can be used with
all receiver-transmitter configurations. Figure 73 illustrates the
connections between the
AD9361
and the BBP for this mode of
operation.
Transmit data is driven on P1_D[11:0] by the BBP such that the
setup and hold times between FB_CLK and data allow the
AD9361
to use FB_CLK to capture the data. Receive data is
driven on P0_D[11:0] by the
AD9361
such that the setup and
hold times between DATA_CLK and data arriving at the BBP
enable the BBP to use DATA_CLK to capture the data. A pulse
on the ENABLE pin (or a rising edge) triggers the beginning of
data transfer, and another pulse (or falling edge) signifies the
end of data transfer.
The Rx_FRAME and Tx_FRAME signals indicate the
beginning of a set (frame) of data samples. Rx_FRAME can be
set to occur once at the beginning of the burst (one high
transition only) for each data transfer, or it can be set to have a
rising edge at the beginning of each frame and repeat with a
50% duty cycle until the data transfer is complete. Similarly,
Tx_FRAME accepts either format from the BBP.
The Tx data samples are carried in two’s complement format.
P1_D[11] is the numerically most significant bit and P1_D[0] is
the least significant bit. The Rx data samples are also carried in
two’s complement format. P0_D[11] is the numerically most
significant bit and P0_D[0] is the least significant bit. In both
cases, the most positive sample value is 0x7FF and the most
negative value is 0x800.
The I and Q data samples are carried on the same data bus in
each direction. For a single RF path in each direction, the data
is carried as follows:
Px: I, Q, I, Q, I, Q, …
For a system with two Rx/Tx channels, the I and Q samples
from RF channels 1 and 2 are carried as follows:
Px: I
1
, Q
1
, I
2
, Q
2
, …
For a system with a 2R1T or a 1R2T configuration, the clock
frequencies, sample periods, and data capture timing are the
same as when configured for a 2R2T system. However, in the
path with only a single channel used, the disabled channel’s I-Q
pair in each data group is unused. These unused slots are
ignored by the
AD9361
. For example, for a 2R1T system using
Tx channel 1, the Tx burst would have two unused slots, as
follows:
The
AD9361
captures P1: I
1
, Q
1
, X, X, …
The unused X slots may be filled with arbitrary data values by
the BBP. Such values could be either constant values, or the
preceding data sample values can be repeated to reduce the bus
switching factor and, therefore, power consumption.
Figure 73. Dual Port Full Duplex Mode (Full Port)
DATA_CLK
RX_FRAME
P1_D[11:0]
FB_CLK
TXNRX
ENABLE
RX
DATA
RX
DATA
TX
DATA
TX
DATA
CTRL
CTRL
PLL
FEEDBACK
CLK GEN
AD9361
BBP
TX_FRAME
P0_D[11:0]
1
1668-
074
Rev. A
