AD9361 Reference Manual
UG-570
| Page 19 of 128
SYNTHESIZER LOOK UP TABLE
Analog Devices provides synthesizer LUTs to generate the static
register writes needed for the VCO and loop filter. There is a set
of tables for FDD operation and a set of tables for TDD
operation. Each set of tables covers the entire VCO frequency
range, as well three different RFPLL loop reference frequencies.
The FDD tables enable the VCO temperature compensation
with the intent that the user will use longer, more accurate
calibration times for the device to remain in operation
indefinitely. In the TDD tables, the temperature compensation
is not enabled, because it is assumed that the VCO will be
calibrated between Tx and Rx frames. If temperature
compensation is required in a TDD operation then the FDD
tables can be used during the TDD synthesizer calibrations.
The provided LUTs are separated into three tables for 40 MHz,
60 MHz, and 80 MHz reference frequencies. The correct table
to use is the one that closest matches the loop F
REF
for the
operating mode. Refer to Table 9 for LUT selection based on
scaled reference frequency.
Table 9.
Lookup Table Reference
RFPLL F
REF
Use Lookup Table
35 MHz to 50 MHz
40 MHz
50 MHz o 70 MHz
60 MHz
70 MHz to 80 MHz
80 MHz
TDD MODE FASTER LOCK TIMES
In TDD mode, the Rx and Tx synthesizers are alternately
turned on and off, following the state of the TXNRX control
line. Typically, the synthesizer is set to trigger a VCO
calibration every time it powers up so that it has a fresh
calibration value. If the LO frequency in TDD does not change
from frame to frame, it is not necessary to recalibrate the VCO
every time. The synthesizers retain the VCO calibration result
even after the synthesizer is powered down. When bursting
between Tx/ALERT/Rx … on the same LO frequency, the
synthesizer only needs to relock and can possibly be completed
in 25 µs or less, depending on the loop bandwidth.
To setup synthesizer in this mode:
1. Setup the VCO for an FDD calibration.
2. Perform VCO calibration.
3. Set the Disable VCO Cal bit.
Step 3 disables the triggering of all VCO calibrations, including
writing of new Integer word. If a new calibration is needed, this
must be cleared.
Note that if the LO frequency is changed, the VCOs will need to
be recalibrated so it will retain the information pertaining to the
new frequency.
EXTERNAL LO
Unlike the internal synthesizers that always operate from 6 GHz
to 12 GHz no matter the RF tune frequency, the frequency
applied when an External LO is used is 2× the desired RF LO
frequency. The range of the EXT LO signal is from 140 MHz to
8 GHz, covering the RF tune frequency range of 70 MHz to
4 GHz. To setup the external LO use the ad9361_trx_ext_
lo_control function.
There are two separate EXT LO inputs, one for Rx and the other
for Tx. The recommended power level for the EXT LO signal at
the
AD9361
pin is −3 dBm ≤ pin ≤ +3 dBm, and the maximum
pin must not 6 dBm.
Note that the EXT_LO_IN package pins are multi-purposed
and they can take on a different functionality (Vtune
measurement) when the device is using internal synthesizers.
See the VCO Vtune Measurement section for information.
BASEBAND PLL (BBPLL)
The BBPLL is a fractional-N synthesizer used to synthesize the
digital clocks for the
AD9361
chip. The BBPLL synthesizes an
integer multiple of the Rx ADC clock, the Tx DAC clock, all
analog calibration clocks, as well as the clocks used in the digital
section. The BBPLL operates of the range of 715 MHz to
1.430 GHz, which allows practically any sample rate to be
generated from any reference frequency. Table 10 is a listing of
common communication systems showing the system sample
rate and the corresponding BBPLL frequency. The output of the
BBPLL drives a programmable divider chain to result in the
desired sample rate and bus communication rate. The required
BBPLL frequency is usually back-calculated by deciding how
the channel filtering will be accomplished and then selecting
the appropriate output divider that allows the BBPLL to operate
within range. Refer to the Filter Guide section for available
filtering and decimation/integration setups.
Table 10. Clock Rates for the Rx and Tx Digital Data Paths
Plus the Appropriate BBPLL Output Frequencies
System
Sample Rate (MSPS)
BBPLL (MHz)
GSM
0.542
832
LTE 1.4
1.92
983.04
LTE 3.0
3.84
983.04
LTE 5
7.68
983.04
LTE 10
15.36
983.04
LTE 15
23.04
737.28
LTE 20
30.72
983.04
WiMAX 1.75
2
1024
WiMAX 3.5
4
1024
WiMAX 4.375
5
1280
WiMAX 7
8
1024
WiMAX 8.75
10
1280
WiMAX 5
5.6
716.8
WiMAX 10
11.2
716.8
WiMAX 20
22.4
1075.2
802.11a
20
1280
802.11n
40
1280
Rev. A
