Board Reference
Signal Name
MAX 10 FPGA Pin
Number
I/O Standard
SW2.2
USER_DIPSW5
F5
3.3 V
Table 3-8: User LED Schematic Signal Names
Board Reference
Signal Name
Color
MAX 10 FPGA Pin
Number
I/O Standard
D3
USER_LED0
Green
C3
3.3 V
D4
USER_LED1
Green
C4
3.3 V
D5
USER_LED2
Green
C5
3.3 V
D6
USER_LED3
Green
D5
3.3 V
D7
USER_LED4
Green
C7
3.3 V
Table 3-9: User Defined I/O Through-Hole Vias
Board Reference
Schematic Signal
Name
MAX 10 FPGA Pin
Number
I/O Standard
Note 1
Description
J12.1
2.5V Power
----
----
Power Supply Connector
for J12
J12.2
2.5V Power
----
----
Power Supply Connector
for J12
J12.3
USER_CLKIN_
IO_P
K22
DIFFIO_RX_R40P
or CLK3P
Dual purpose pin. Either
User I/O or Clock input
ref. for this group of
LVDS channels
J12.4
USER_LVDS_P2
Y17
DIFFIO_TX_RX_
B43P, High Speed
LVDS User I/O_2. Note 1
J12.5
USER_CLKIN_
IO_N
K21
DIFFIO_RX_
R40N or CLK3N
Dual purpose pin. Either
User I/O or Clock input
ref. for this group of
LVDS channels
J12.6
USER_LVDS_N2 AA17
DIFFIO_TX_RX_
B43N, High Speed
LVDS User I/O_2. Note 1
J12.7
GND
----
----
Ground Reference for this
group of I/Os
J12.8
GND
----
----
Ground Reference for this
group of I/Os
UG-20006
2016.02.29
General User Input/Output
3-9
Board Components
Altera Corporation
Send Feedback