Setup Elements
Table 3-4: Board Settings DIP Switch and Jumper Schematic Signals
Board Reference
Signal Name
Device / Pin Number
I/O Standard
SW2.3
MAX10_CONFIG_SEL MAX 10 / H10
3.3V
SW2.4
MAX10_BYPASSn
MAX II / B20
3.3V
Table 3-5: Board Settings Push Button Signal Names
Board Reference
Signal Name
MAX 10 FPGA Pin
Number
I/O Standard
S6
MAX10_nCONFIG
H9
3.3V
S7
MAX10_RESETn
D9
3.3V
General User Input/Output
User-defined I/O signal names, FPGA pin numbers, and I/O standards for the MAX 10 FPGA 10M50
Evaluation Board.
Table 3-6: User-Defined Push Button Signal Names
Board Reference
Signal Name
MAX 10 FPGA Pin
Number
I/O Standard
S1
USER_PB0
R20
1.2 V
S2
USER_PB1
Y20
1.2 V
S3
USER_PB2
Y21
1.2 V
S4
USER_PB3
U20
1.2 V
Table 3-7: User-Defined DIP Switch Schematic Signal Names
Board Reference
Signal Name
MAX 10 FPGA Pin
Number
I/O Standard
SW1.1
USER_DIPSW0
R18
1.2 V
SW1.2
USER_DIPSW1
T19
1.2 V
SW1.3
USER_DIPSW2
T18
1.2 V
SW1.4
USER_DIPSW3
U19
1.2 V
SW2.1
USER_DIPSW4
G4
3.3 V
3-8
Setup Elements
UG-20006
2016.02.29
Altera Corporation
Board Components
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