Chapter 17
Timer and Counter Instructions
17–10
Important: This instruction provides high–speed counting on fixed
controllers with 24 VDC inputs. One HSC instruction
allowed per controller. To use the instruction, you must clip a
jumper as described in the installation manual, catalog number
1747–NI002. Input I:0/0 then operates in the high–speed mode.
The address of the high–speed counter enable bit is C5:0/CU.
When rung conditions are true, C5:0/CU is set and transitions
occurring at input I:0/0 are counted. The maximum pulse rate is
8 kHz.
Do not program an XIC instruction with the I:0/0 address and
the HSC instruction as the output. This will enable and disable
the high–speed counter –missing counts. Instead, use an
unconditional rung with the HSC instruction, or use a condition
that only prevents the HSC instruction from counting.
To begin high–speed counting, load a preset value into C5:0.PRE and enable
the counter rung. To load a preset value, do one of the following:
•
Change to the Run or Test mode from another mode.
•
Power up the processor in the Run mode.
•
Reset the HSC using the RES instruction.
Automatic reloading occurs when the HSC itself sets the DN bit on interrupt.
Each input transition that occurs at input I:0/0 will cause the accumulator of
the HSC to increment. When the accumulator value equals the preset value,
the done bit (C5:0/DN) will be set, the accumulator will be cleared, and the
preset value (C5:0.PRE) will be loaded into the HSC in preparation for the
next high–speed transition at input I:0/0. The ladder program polls the done
bit (C5:0/DN) to determine the state of the HSC. Once the done bit has been
detected as set, the ladder program should clear bit C5:0/DN (use the unlatch
OTU instruction) before the HSC accumulator again reaches the preset value,
or the overflow bit (C5:0/OV) will be set.
It is important to note that the HSC differs from the CTU and CTD counters
in that the HSC is a hardware counter as opposed to a software counter and
that the HSC operates asynchronously to the ladder program scan. The HSC
accumulator value (C5:0.ACC) is normally updated each time the HSC rung
is evaluated in the ladder program (this means that the HSC hardware
accumulator value is transferred to the HSC software accumulator). Many
HSC counts could occur between HSC evaluations which would make
C5:0.ACC inaccurate when used throughout a ladder program. To allow for
an accurate HSC accumulator value, the update accumulator bit (C5:0/UA)
will cause C5:0.ACC to be immediately updated to the state of the hardware
accumulator when set. (Use the OTE instruction only to reset the UA bit.)
Note: The HSC instruction will immediately clear bit C5:0/UA following the
accumulator update.
The high–speed counter can be reset using the RES instruction at address
C5:0. A reset will clear the HSC status bits, clear the accumulator, and load
the preset value into the counter.
