Chapter 17
Timer and Counter Instructions
17–9
CTD instructions also count false-to-true rung transitions. The counter
accumulated value is decremented one count for each false-to-true transition.
When a sufficient number of counts has occurred and the accumulated value
becomes less than the preset value, the counter done bit (bit 13) is reset.
Bit 14 of the counter control word is the count down enable (CD) bit. It is
set when rung conditions of the CTD instruction are true. It is reset when
either rung conditions go false (count down instruction disabled) or the
appropriate reset instruction is enabled.
When a CTD instruction counts beyond its preset value and reaches a count
of (–32,768 – 1), the underflow bit (UN) is set. You can reset it by
energizing the appropriate RES instruction. You can also reset the underflow
bit by incrementing the count greater than or equal to –32,768 with a CTU
instruction having the same address as the CTD instruction.
When the UN bit is set, the accumulated value wraps around to +32,767 and
continues counting down from there.
Fixed Controllers Only
High-Speed Counter
HSC
Output Instruction
(HSC)
(CU)
(DN)
HSC
HIGH–SPEED COUNTER
Counter
C5:0
Preset
800
Accum
0
F1
F2
F3
F4
F5
ZOOM on HSC –(HSC)– 2.0.0.0.2
NAME: HIGH–SPEED COUNTER
COUNTER: C5:0
PRESET: 800
ACCUM: 0
CU CD DN OV UN UA
0 0 0 0 0 0
EDT_DAT
HHT Ladder Displays:
HHT Zoom Displays:
Ladder Diagrams and APS Displays:
(online monitor mode)
The High–Speed Counter is a variation of the CTU counter. The HSC
instruction is enabled when the rung logic is true and disabled when the rung
logic is false.
High-Speed Counter (HSC)
