Chapter 20
Math Instructions
20–2
Using Arithmetic Status Bits
After an instruction is executed, the arithmetic status bits in the status file are
updated:
•
Carry (C), S:0/0 – Set if a carry is generated; otherwise cleared.
•
Overflow (V), S:0/1 – Indicates that the actual result of a math
instruction does not fit in the designated destination.
•
Zero (Z), S:0/2 – Indicates a 0 value after a math, move, or logic
instruction.
•
Sign (S), S:0/3 – Indicates a negative (less than 0) value after a math,
move, or logic instruction.
Overflow Trap Bit, S:5/0
The minor error bit is set upon detection of a mathematical overflow or
division by 0. If this bit is still set upon execution of the END statement, a
TND instruction, or an REF instruction, a recoverable major error will be
declared.
In applications where a math overflow or a division by 0 will occur, you can
avoid a major error from occurring by resetting S:5/0 with an unlatch (OTU)
instruction in your program. The rung containing the OTU instruction must
be between the overflow point and the END statement, or TND instruction,
or REF instruction.
Math Register, S:14 and S:13
Status word S:13 contains the least significant word of the 32-bit values of
MUL and DDV instructions. It contains the remainder for DIV and DDV
instructions. It also contains the first four BCD digits for the FRD and TOD
instructions.
Status word S:14 contains the most significant word of the 32-bit values of
MUL and DDV instructions. It contains the unrounded quotient for DIV and
DDV instructions. It also contains the most significant digit (digit 5) for
TOD and FRD instructions.
Indexed Word Addresses
With SLC 5/02 processors, you have the option of using indexed word
addresses for instruction parameters specifying word addresses. Indexed
addressing is discussed in chapter 4.
