Akai PDP4225M, Руководство по обслуживанию, Страница: 54 / 77

A im s i
Absolute Maximum Ratings*
O pe ra ting T e m p e ra tu re ........................ ............. -55 °C to + 1 2 5 °C
S tora ge T e m p e ra tu re ............................ ............. -65 °C to + 1 50°C
V oltage on A n y Pin
w ith R espect to G r o u n d ....................... .................. -1 .0 V to + 7 .0 V
M a xim u m O pe ra tin g V o lta g e ............. .................................. 6.2 5 V
DC O utpu t C u rre n t................................. ................................5.0 m A
*N O T IC E : S tre sse s be yond th o s e listed un de r “A b so lu te
M axim um R a ting s” m ay ca u se p e rm a n e n t d a m ­
age to th e device. T his is a s tre s s rating on ly and
fu n c tio n a l op era tion of th e de vice at th e s e or any
o th e r co n d itio n s beyond th o s e in dicated in th e
op e ra tio n a l s e c tio n s of this sp e c ific a tio n is not
im plied. E xposure to a b so lu te m axim um rating
c o n d itio n s fo r exte nde d p e rio d s m ay affect
device reliability.
Block Diagram
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive
edge clock data into each EEPROM device and negative
edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for
serial data transfer. This pin is open-drain driven and may
be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1
and A0 pins are device address inputs that are hard wired
or left not connected fo r hardw are c o m p a tib ility with
AT24C16. When the pins are hardwired, as many as eight
32K/64K devices may be addressed on a single bus sys­
tem (device addressing is discussed in detail under the
Device Addressing section). When the pins are not hard­
wired, the default A2, A1, and A0 are zero.
WRITE PROTECT (WP): The write protect input, when tied
to GND, allows normal write operations. When WP is tied
high to VCC, all write operations to the upper quandrant
(8/16K bits) of memory are inhibited. If left unconnected,
WP is internally pulled down to GND.
Memory Organization
AT24C32/64, 32K/64K SERIAL EEPROM: The 32K/64K is
internally organized as 256 pages of 32 bytes each. Ran­
dom word addressing requires a 12/13 bit data word
address.
AT24C32/64
5 0 / 7 3