Akai PDP4225M, Руководство по обслуживанию, Страница: 53 / 77

Features
• Low-Voltage and Standard-Voltage Operation
- 5.0 (VCC = 4.5V to 5.5V)
- 2.7 (VCC = 2.7V to 5.5V)
- 2.5 (VCC = 2.5V to 5.5V)
- 1.8 (VCC = 1.8V to 5.5V)
Low-Power Devices (ISB = 2 pA @ 5.5V) Available
Internally Organized 4096 x 8, 8192 x 8
2-Wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Clock Rate
Write Protect Pin for Hardware Data Protection
32-Byte Page Write Mode (Partial Page Writes Allowed)
Self-Timed Write Cycle (10 ms max)
High Reliability
- Endurance: 1 Million Write Cycles
- Data Retention: 100 Years
- ESD Protection: >3,000V
• Automotive Grade and Extended Temperature Devices Available
• 8-Pin JEDEC PDIP, 8-Pin JEDEC SOIC, 8-Pin EIAJ SOIC,
and 8-pin TSSOP Packages
Description
The AT24C32/64 provides 32,768/65,536 bits of serial electrically erasable and pro­
grammable read only memory (EEPROM) organized as 4096/8192 words of 8 bits
each. The device’s cascadable feature allows up to 8 devices to share a common 2-
wire bus. The device is optimized for use in many industrial and commercial applica­
tions where low power and low voltage operation are essential. The AT24C32/64 is
available in space saving 8-pin JEDEC PDIP, 8-pin JEDEC SOIC, 8-pin EIAJ SOIC,
and 8-pin TSSOP (AT24C64) packages and is accessed via a 2-wire serial interface.
In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V),
2.5V (2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
Pin Configurations
Pin Name Function
A 0 - A2 A d d re s s Inputs
S D A S erial Data
S C L S erial C lo ck Input
W P W rite Protect
8-P in T S S O P
A0 [
A1 [
A2 [
GND [
2 o
8 ZD VCC
7 ZD
WP
3 6 ZD
SCL
4
5 ZD SDA
8-P in PDIP
8-P in S O IC
A0 H 1
W
8 □ VCC
A0 d 1 8 d VCC
A1 H 2 7 □ WP
A1 d 2 7 □ WP
A2 H 3 6 □ SCL
A2 d 3 6 d SCL
GND H 4 5 □ SDA
GND d 4 5 d SDA
2-Wire
Serial EEPROM
32K (4096 x 8)
64K (8192 x 8)
AT24C32
AT24C64
Rev. 0336G-04/01
4 9 / 7 3