Status Subsystem
88
Series N6700 User’s Guide
does a serial poll, RQS is cleared inside the register and returned in
bit position 6 of the response. The remaining bits of the Status Byte
register are not disturbed.
MAV Bit and Output Queue
The Output Queue is a first-in, first-out (FIFO) data register that
stores power system-to-controller messages until the controller reads
them. Whenever the queue holds one or more bytes, it sets the MAV
bit (4) of the Status Byte register.
LOGICAL
OR
LOGICAL
OR
PON
CME
EXE
DDE
QYE
OPC
0
2
3
4
5
7
1
4
8
16
32
128
1
4
8
16
32
128
EVENT
ENABLE
STANDARD EVENT
STATUS
ERROR QUEUE
QUEUE
NOT
EMPTY
Error
Error
Error
STATUS BYTE
SERVICE
REQUEST
ENABLE
LOGICAL
OR
SERVICE
REQUEST
GENERATION
8
16
32
128
8
16
32
128
RQS
OPER
MSS
ESB
MAV
QUES
4
5
6
7
UNR
OT
OV
0
4
QUESTIONABLE STATUS
(IDENTICAL REGISTERS FOR EACH CHANNEL)
10
CONDITION
LOGICAL
OR
EVENT
ENABLE
QSUM
CHAN 1
SAME
AS
CHAN 1
LOGICAL
OR
PTR/NTR
1
16
1024
1
16
1024
1
16
1024
1
16
1024
3
LOGICAL
OR
CHAN 2
CHAN 3
CHAN 4
QSUM
QSUM
QSUM
CHAN 2
CHAN 3
CHAN 4
OSUM
CONDITION
0
2
PTR/NTR
EVENT
ENABLE
1
CV
CC
SAME
AS
CHAN 1
CHAN 1
OSUM
OSUM
1
2
4
OC
1
OFF
OSUM
OPERATION STATUS
(IDENTICAL REGISTERS FOR EACH CHANNEL)
PF
2
4
4
2
4
4
2
2
2
CP+
3
8
8
8
8
CP -
5
32
32
32
32
INH
9
512
512
512
512
64
4
3
WTG
8
16
1
2
4
8
16
1
2
4
8
16
1
2
4
8
16
WTG
OUTPUT QUEUE
QUEUE
NOT
EMPTY
Data
Data
Data
2
ERR
meas
trans
4
4
*STB?
*SRE<n>
*SRE?
*ESR?
STAT:QUES:COND?
*ESE<n>
*ESE?
SYST:ERR?
STAT:QUES:PTR |:NTR <n>
STAT:QUES:PTR |:NTR ?
STAT:QUES:EVEN?
STAT:QUES:ENAB <n>
STAT:QUES:ENAB?
STAT:OPER:COND?
STAT:OPER:EVEN?
STAT:OPER:ENAB <n>
STAT:OPER:ENAB?
STAT:OPER:PTR |:NTR <n>
STAT:OPER:PTR |:NTR ?
PROT
11
2048
2048
2048
2048
