ADM5120
Register Description
4.7.20 MPMC Dynamic Ras Cas[0,1,2,3] register
Note:
offset = 200h, 220h, 240h is for SMC_CSZ0, SMC_CSZ1, and SMC_CSZ2
respectively
Bit # Type Name
Descriptions
Initial Value
1:0
R/W RAS
RAS latency (active to read or write delay):
11
00=reserved
01=one clock cycle(a)
10=two clock cycles
11=three clock cycles (reset value on nPOR).
7:2
Reserved
Read undefined, must be written as zeros.
9:8 R/W
CAS
CAS
latency:
00=reserved
01=one clock cycle(a)
10=two clock cycle
11=three clock cycle(reset value on nPOR).
11
31:10
Reserved
Read undefined, must be written as zeros.
Note:
The RAS to CAS latency (RAS) and CAS latency (CAS) are both defined in MPMCCLK
cycles.
4.7.21 MPMC Static Config[0,1,2,3] register
Note:
offset = 200h, 220h is for F_CS1_N and F_CS0_N respectively.
ADMtek Inc.
4-46
Bit # Type Name
Descriptions
Initial Value
1:0 R/W
MW
Memory
width:
00 = 8bit 01 = 16bit
10 = 32bit
11 = reserved.
The value of the F_CS0_N controlled memory width
field is determined by reset latched value of A[18:17]
00(default
value for
SMC_CSZ0,
SMC_CSZ2,
SMC_CSZ3)
2
Reserved
Read undefined, must be written as zeros.
3 R/W
PM
Page
mode:
0=disabled (reset value on nPOR)
1=async page mode four enabled.
0
5:4
Reserved
Read undefined, must be written as zeros.
6 R/W
Unaffected by AHB reset (HRESETn).
PC
Chip
select
polarity:
0 = active LOW chip select
1 = active HIGH chip select.
The value of the chip select polarity on power-on-reset
(nPOR) is determined by the relevant MPMCSxPOL
signal. This value can be overridden by software. This
field is
7
R/W PB
Byte lane state:
0 = For reads all the bits in nMPMCBLSOUT[3:0] are
0
