XVME-6500
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 19 -
http://www.acromag.com
- 19 -
www.acromag.com
SW4-5 will disable the PON_FSM micro-sequencer. The micro-sequencer
allows the power-up value of the CR/CSR registers to be automatically set-up
by the PON_FSM controller without intervention of local intelligence. Please
refer to Technical User Guide for more information.
SW4-6 will enable the propagation of a local reset (restarting the OS or pushing
the front panel reset button) to the VME SYSRESETn signal on the VME
backplane.
SW4-7 and SW4-8 are for the SPI flash write protest and SPI programming
enable signals. The SPI flash contains the firmware for the FPGA; therefore,
these two signals should always be kept enabled unless stated otherwise in
Acromag documentation.
3.1.4 JTAG VREF Configuration Switch SW5
Table 3.1.d summarizes the functions, settings, and descriptions for dip switch
SW5.
Table 3.1.d: JTAG VREF Configuration Switch SW5
JTAG VREF Configuration Switch SW5
Position
Function
Switch Setting
Description
1-3
Lower Site
(J8) JTAG VREF
Configuration
1-2 (default)
Lower Site VREF = 3.3V
2-3
Lower Site VREF = 2.5V
4-6
Upper Site
(J9) JTAG VREF
Configuration
4-5 (default)
Upper Site VREF = 3.3V
5-6
Upper Site VREF = 2.5V
SW5 is used to select the VREF voltage for the XMC/PMC JTAG connections on
J8 and J9.
