INDUSTRIAL I/O PACK SERIES APCe8650
PCI BUS CARRIER BOARD
Acromag, Inc. Tel: 248-295-0310
- 12 -
www.acromag.com
DATA TRANSFER TIMING
The PCI express interface will treat all data transfers as 32 bits with the
appropriate byte lanes enabled to support the actual requested number of
bytes: 4, 2 or 1. The 32 bit transfer is broken into two back to back 16 bit
accesses on the IP bus. The highest transfer rates will be achieved when
accessing two 16 bit IP registers with consecutive addresses. The time to
complete the 32 bit PCI express transaction is the same for 4, 2 or 1 byte(s)
transferred. The time between PCI express transactions is system dependent.
The APCe8650 does not insert any hold states.
3.
PROGRAMMING INFORMATION
This Section provides the specific information necessary to program and
operate the APCe8650 non-intelligent carrier board.
This Acromag APCe8650 is a PCIe Specification version 1.1 compliant PCIe bus
slave carrier board. The carrier connects a PCIe host bus to the IP module’s
16-bit data bus per the Industrial I/O Pack logic interface specification on the
mezzanine (IP) boards that are installed on the carrier.
The PCI bus is defined to address three distinct address spaces: I/O, memory,
and configuration space.
The IP modules can be accessed via the PCI bus
memory space only.
The PCIe card’s configuration registers are initialized by system software at
power-up to configure the card. The PCIe carrier is a Plug-and-Play PCI card.
As a Plug-and-Play card the board’s base address and system interrupt
request line are not selected via jumpers but are assigned by system software
upon power-up via the configuration registers. A PCIe bus configuration
access is used to access a PCIe card’s configuration registers.
PCI Configuration Address Space
When the computer is first powered-up, the computer’s system configuration
software scans the PCIe bus to determine what PCIe devices are present. The
software also determines the configuration requirements of the PCIe card.
The system software accesses the configuration registers to determine how
many blocks of memory space the carrier requires. It then programs the
carrier’s configuration registers with the unique memory address range
assigned.
The configuration registers are also used to indicate that the PCI carrier
requires an interrupt request line. The system software then programs the
configuration registers with the interrupt request line assigned to the PCI
carrier.
Since this PCI carrier is portable and not hardwired in address space, this
carrier’s device driver provided by Acromag uses the mapping information
stored in the carrier’s Configuration Space registers to determine where the
carrier is mapped in memory space and which interrupt line will be used.
