Acromag AcroPack AP560, Руководство пользователя

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AcroPack Series AP560 CAN Bus Interface Module
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Channel x Command Register, (Read/Write) - (BAR0 + Chan X base + 00H)
A write to this register triggers the serial transmission of the SPI instruction
from the FPGA to the HI3111 CAN controller. Any additional data bytes
required for the selected instruction are also transmitted.
The function of each of the command register bits are described in Table
9Table .
Table 10 Command Register
BIT FUNCTION
7:0 SPI Instruction – this 8-bit command is
transferred serially to the HI3111
31:8 Not Used
1
Notes (Table 8):
1. All bits labeled “Not Used” will return logic “0” when read.
Channel x Control Register, (Read/Write) - (BAR0 + Chan X base + 04H)
The function of each of the control register bits are described in Table 11.
Table 11 Control Register
BIT FUNCTION
0 Frequency Select – selects the frequency
of the oscillator input to the CAN
controller. This is the f
OSC
used in the bit
rate calculation.
0 – 32 MHz
1 – 40 MHz
31:1 Not Used
1
Notes (Table 11):
1. All bits labeled “Not Used” will return logic “0” when read.
Channel x Interrupt Register, (Read/Write) - (BAR0 + Chan X base + 08H)
This read/write register is used to enable interrupts by channel.
The function of the channel interrupt register bit is described in Table 10. A
power-up or system reset sets all interrupt register bits to 0.
Table 12 Channel Interrupt Register
BIT FUNCTION
0 Channel X CAN controller Interrupt Enable Bit - This bit
must be set to logic “1” to enable generation of interrupts
from the Channel X CAN controller. Setting this bit to logic
“0” will disable this interrupt. (Read/Write Bit)
31:1 Not Used
Notes (Table 10):
1. All bits labeled “Not Used” will return logic “0” when read .