Acromag AcroPack AP560, Руководство пользователя

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AcroPack Series AP560 CAN Bus Interface Module
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REGISTERS
Each of the four HI3111 CAN controllers on the AP560 has fourteen register
for control and status. The addresses listed in the following table are offsets
from each channels’ base address.
This section describes the HI-3111 registers. All register bits are active high.
Unless otherwise indicated, all registers are reset in software to the logic zero
condition after Master Reset:
REGISTER R/W DESCRIPTION WRITE
OP-CODE
READ
OP-CODE
CTRL0 R/W Control Register 0 0x14 0xD2
CTRL1 R/W Control Register 1 0x16 0xD4
BTR0 R/W Bit Timing Register 0 0x18 0xD6
BTR1 R/W Bit Timing Register 1 0x1A 0xD8
TEC R/W Transmit Error Counter Register 0x26 0xEC
REC R/W Receive Error Counter Register 0x24 0xEA
MESSTAT R Message Status Register N/A 0xDA
ERR R Error Register N/A 0xDC
INTF R Interrupt Flag Register N/A 0xDE
INTE R/W Interrupt Enable Register 0x1C 0xE4
STATF R Status Flag Register N/A 0xE2
TIMERUB R Free-Running Timer Upper Byte
Register N/A 0xFA
TIMERLB R Free-Running Timer Lower Byte
Register N/A 0xFA
Note: Free-running counter registers, TIMERUB:TIMERLB are read with a
single Op-Code (0xFA) as a 16-bit value.