Acromag AcroPack AP560, Руководство пользователя

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AcroPack Series AP560 CAN Bus Interface Module
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Channel x Output Message Registers, (Read/Write) - (BAR0 + Chan X base + 10H thru 1CH)
Write the data bytes to these registers prior to writing the command register.
The function of each of the control register bits are described in Table 13
Output Message Register
Table 13 Output Message Registers
Bits
Addr 31 24 23 16 15 8 7 0
10 Byte 3 Byte 2 Byte 1 Byte 0
14 Byte 7 Byte 6 Byte 5 Byte 4
18 Byte 11 Byte 10 Byte 9 Byte 8
1C Not used Not used Byte 13 Byte 12
Channel x Input Message Registers, (Read/Write) - (BAR0 + Chan X base + 20H thru 2CH)
You can read the data bytes from these registers after writing the command
register and waiting for the busy bit to clear.
The function of each of the control register bits are described in Table 14
Input Message Registers.
Table 14 Input Message Registers
Bits
Addr 31 24 23 16 15 8 7 0
20 Byte 3 Byte 2 Byte 1 Byte 0
24 Byte 7 Byte 6 Byte 5 Byte 4
28 Byte 11 Byte 10 Byte 9 Byte 8
2C Byte 15 Byte 14 Byte 13 Byte 12
XADC Status/Control Register (Read/Write) - (Base + 60H)
This read/write register will access the XADC register at the address set in the
XADC Address Register allowing the module’s key supply voltages and FPGA
junction temperature to be monitored.
For example, the address of the XADC Status register that is to be accessed is
first set via the XADC Address register at Base plus 0x64H. Next, this register
at Base plus 60H is read. Bits 22 to 16 of this register hold the address of the
XADC register that is accessed. Data bits 15 to 6 of this register hold the
“ADCcode” temperature, Vccint, or Vccaux value. Data bits 5 to 0 are not
used. Valid addresses are given in column one of the table below.
Reading or writing this register is possible via 32-bit data transfers.