SERIES AP445 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 31 - http://www.acromag.com
- 31 -
www.acromag.com
Appendix B
Figure 1 AP445 Block Diagram
FPGA
Xilinx Artix 7
P2
F
I
E
L
D
O
U
T
P
U
T
S
FLASH
MEMORY
+3.3V
FIELD
ISOLATION
AP LOGIC
NON-ISOLATED
GND
+3.3V
ACROPACK
LOGIC
INTERFACE
SUPPLY0
COM0
OD00
R
NO POP
I/O
INTERFACE
SIMPLIFIED OUTPUT
CHANNEL
*A PORT CONTAINS 8 OUTPUTS
THAT SHARE SUPPLY/COM
C
A
x1 PCIe
AP445 BLOCK DIAGRAM
P1
OUTPUT BUS
OD31
FIGURE 1: AP445 Block Diagram
Figure 2 AP445 Digital Out to AP440 Digital In
COM
ODXX
COM
SUPPLY
INXX
5V
470
AP440 INPUT
INPUT: 4-18V
AP445 OUTPUT
AP445 DIGITAL OUT TO AP440 DIGITAL INPUT
WHEN INTERFACING DIGITAL OUTPUT LEVELS TO THE AP440., USE THE
MODEL AP440-1 (4V THRESHOLD) AND ADJUST THE EXTERNAL PULLUP
VALUE ACCORDINGLY.
470 OHM PULLUPS SHOULD BE INSTALLED ON THE AP445.
WHEN INTERFACING THE AP445 TO A TYPICAL TTL INPUT DEVICE LIKE THE
74LS541. THE 4.7K PULLUPS SHOULD BE INSTALLED AND THE
CONNECTED TO THE PART SUPPLY PIN.
P2 PINOUTS OF THE AP440 AND AP445 ARE DIRECTLY COMPATABLE.
HOWEVER, THE AP445INCLUDES A PULLUP SUPPLY PIN FOR EACH PORT
AT PIN 5 (PORT0), PIN 15 (PORT 1), PIN 25 (PORT 2), AND PIN 35 (PORT 3).
THESE PINS ARE NOT CONNECTED ON THE AP440.
AP440 INPUTS AND AP445 OUTPUTS ARE BIPOLAR AND MAY BE
CONNECTED IN ANY DIRECTION WITH RESPECT TO PORT COMMON.
FIGURE 2: AP445 DIGITAL OUT TO AP440 DIGITAL IN
