SERIES AP445 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 17 - http://www.acromag.com
- 17 -
www.acromag.com
Table 3.1: Configuration
Registers
Reg.
Num.
D31 D24
D23 D16
D15 D8
D7 D0
0
Device ID
0x7014 AP445E-LF
Vendor ID
16D5
1
Status
Command
2
Class Code=118000
Rev ID=00
3
BIST
Header
Latency
Cache
4
64-bit Memory Base Address for Memory Accesses to PCIe
interrupt and I/O registers
4K Space (BAR0)
5:10
Not Used
11
Subsystem ID
0x7014 AP445E-LF
Subsystem Vendor ID
16D5
12
Not Used
13,14
Reserved
15
Max_Lat
Min_Gnt
Inter. Pin
Inter. Line
This board is allocated a 4K byte block of memory (BAR0), to access the PCIe
interrupt and I/O registers. The PCIe bus decodes 4K bytes for BAR0 for this
memory space.
The memory space address map for the AP445 is shown in Table 3.2. Note
that the base address for the board (BAR0) in memory space must be added
to the addresses shown to properly access these AP445 registers. Register
accesses as 32, 16, and 8-bit data in memory space are permitted.
Memory Map
The AP445 registers provide simple control and readback of 32 digital
output lines. Data is read from or written to one of four groups (ports) as
designated by the address and read and write signals.
Table 3.2: AP445
Memory Map
Notes:
1. The AP will respond to
addresses that are “Not
Used”. The board will
return “0” for all address
reads that are not used or
reserved.
BAR0 Base Address
Bit(s)
Description
0x0000 0000
32:0
Reset Register
0x0000 0004
32:0
Location in System Register
0x0000 0008
32:0
Port Output Register
OUTPUT00-OUTPUT31
0x0000 000C→
0x0000 0044
32:0
NOT USED
1
0x0000 0048
32:0
XADC Status Control Register
0x0000 004C
32:0
XADC Address Register
