
IEC15000393-2-en.vsdx
U_CATENARY_G2AI1
G1AI2P
G1N
G1AI1
G1AI2
G1AI3
G1AI4
SMAI2
BLOCK
G2AI2P
O:1IT:3II:2
G2N
GRP2L1
G2AI1
GRP2L2
G2AI2
GRP2L1L2
G2AI3
GRP2N
G2AI4
TRM_40.CH1(I) I_CATENARY
TRM_40.CH2(I)
TRM_40.CH7(U) U_CATENARY
TRM_40.CH8(U) U_FEEDER
CURRENTS_G1AI2P
I_CATENARY_G1AI1
I_AT_NEUTRAL_G1N
SMAI1
BLOCK
O:1IT:3II:1
GRP1L1
GRP1L2
GRP1L1L2
GRP1N
VOLTAGES_G2AI2P
U_FEEDER_G2AI2
I_FEEDER
TRM_40.CH3(I) I_AT_NEUTRAL
PRE PROCESSING
I_FEEDER_G2AI2
ZRCPDIS
I2P*
U2P*
BLOCK
VTSZ
BLKTR
BLKZ1
BLKZ2
BLKZ3
BLKZ4
BLKZ5
EXTRELZ1
EXTRELZ2
EXTRELZ3
EXTRELZ4
EXTRELZ5
TRIP
TRZ1
TRZ2
TRZ3
TRZ4
TRZ5
START
STZ1
STZ2
STZ3
STZ4
STZ5
STNDZ1
STNDZ2
STNDZ3
STNDZ4
STNDZ5
STFW
STRV
ZMAG
RMAG
XMAG
ZRCPDIS_TR
DISTANCE PROTECTION
I_CATENARY_G1AI1
I_FEEDER_G2AI2
I_AT_NEUTRAL_G1N
U_CATENARY_G2AI1
U_FEEDER_G2AI2
A1RADR
^GRPINPUT1
^GRPINPUT2
^GRPINPUT3
^GRPINPUT4
^GRPINPUT5
^GRPINPUT6
^GRPINPUT7
^GRPINPUT8
^GRPINPUT9
^GRPINPUT10
ANALOG
DISTURBANCE
RECORDER
BACK UP OVER CURRENT PROTECTION
I_FEEDER>
I_FEEDER>_CURRENT
I_FEEDER>_START
D2PTOC
I2P*
U2P*
BLOCK
BLKST1
BLKTR1
BLKST2
BLKTR2
TRIP
TRSTP1
TRSTP2
START
STSTP1
STSTP2
ST2NDHRM
DIR1
DIR2
UDIRLOW
CURRENT
VOLTAGE
UIANGLE
CURRENTS_G1AI2P
VOLTAGES_G2AI2P
D2PTOC
I2P*
U2P*
BLOCK
BLKST1
BLKTR1
BLKST2
BLKTR2
TRIP
TRSTP1
TRSTP2
START
STSTP1
STSTP2
ST2NDHRM
DIR1
DIR2
UDIRLOW
CURRENT
VOLTAGE
UIANGLE
I_CATENARY>
CURRENTS_G1AI2P
VOLTAGES_G2AI2P
I_CATENARY>_CURRENT
I_CATENARY>_START
EF2PTOC
I2P*
U2P*
I2PDIR*
BLOCK
BLKTR
BLKST1
BLKST2
TRIP
TRSTP1
TRSTP2
TRDIRFW
START
STSTP1
STSTP2
STFW
STRV
ST2NDHRM
I_AT_N>
CURRENTS_G1AI2P
VOLTAGES_G2AI2P
CURRENTS_G1AI2P
I_AT_N>_START
RWRFLO PHASE TRIGGERING LOGIC
REALCOMP
INPUT
REF
INEQUAL
INHIGH
INLOW
INV
INPUT
OUT
OR
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
OUT
NOUT
AND
INPUT1
INPUT2
INPUT3
INPUT4
OUT
NOUT
RWRFLO
PHSELL1*
PHSELL2*
CALCDIST*
CALCMADE
FLINVAL
FLT_DIST
FLT_X
FLT_R
FLT_LOOP
DISTL1E
SECTL1E
FLTRL1E
FLTXL1E
DISTL2E
SECTL2E
FLTRL2E
FLTXL2E
DISTL1L2
SECTL1L2
FLTRL1L2
FLTXL1L2
I_CATENARY>_CURRENT
I_FEEDER>_CURRENT
I_AT_N>_START
I_CATENARY>_START
I_FEEDER>_START
OR
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
OUT
NOUT
AND
INPUT1
INPUT2
INPUT3
INPUT4
OUT
NOUT
ZRCPDIS_TR
I_REALCOMP_INEQUAL
I_REALCOMP_INHIGH
I_REALCOMP_INLOW
INV_I_AT_N>_START
I_REALCOMP_INEQUAL
I_REALCOMP_INEQUAL
I_REALCOMP_INHIGH
I_REALCOMP_INLOW
INV_I_AT_N>_START
INV_I_AT_N>_START
IEC18000068 V1 EN-US
Figure 35:
ACT configuration in PCM600 for ATCatenary type
Verifying the case SystemType = 2Phase
GUID-3E43344B-B8FB-4E46-9AB8-410D45155131 v2
1.
Apply the voltage and current as shown in Table
Table 30:
Pre-fault voltages and current
Signal
Magnitude (Volts)
Angle (Degrees)
1
UL
IECEQUATION15084 V1 EN-US
55
0
2
UL
IECEQUATION15085 V1 EN-US
55
180
1
IL
IECEQUATION15086 V1 EN-US
0
0
2
IL
IECEQUATION15087 V1 EN-US
0
180
2.
Wait for a few seconds and apply voltage and current according to Table
depending on
which fault loop is to be verified.
1MRK 506 377-UEN Rev. K
Section 10
Testing functionality by secondary injection
Railway application RER670
147
Commissioning manual
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Содержание Relion 670 series
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