10. Parallel I/O
94
7
6
5
4
3
2
1
0
0
0
0
0
0
Port Port Port
2
1
0
Debounce
0 Disable†
1 Enable
Register: Debounce Configure
Mode: Enhanced (Bank 2)
Address: 78h
Access: Read and Write
Debounce Configure Register
Note:
This register controls whether each individual port or the external sense inputs
are passed through the debounce logic before being recognized.
7
6
5
4
3
2
1
0
0
0
Port
Port
Port
2
1
0
Port
2
Port
1
Port
0
Duration
00 4
µ
s
01 64
µ
s
10 1 ms
11 8 ms
Register: Debounce Duration
Mode: Enhanced (Bank 2)
Address: 79h
Access: Read and Write
Debounce Duration Register
Note:
This register controls the duration required by each input signal before it is
recognized by each individual input. Default values are 00, setting a 4
µ
m debounce
period.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
Register: Debounce Clock
Mode: Enhanced (Bank 2)
Address: 7Bh
Access: Write
Debounce Clock Register
†
On power up or reset, these bits are set to 0.
