6. DMA Controller
63
DMA Command Registers
The DMACMD1 resister is used to enable both channels and to select the rotating
method for changing the bus priority control structure. Under all prioritization schemes,
the DRAM refresh control unit receives highest priority.
REGISTER:
ADDRESS:
AT ADDRESS:
ACCESS:
D7
D6
D5
D4
D3
D2
D1
D0
DMACMD1
0F008h
W/O
Reserved, write 0's to these bits
1= Enables both DMA channels
Reserved, write 0 to this bit
Reserved
0
Reserved
0
0
0= Disable both DMA channels
1= Enable priority rotation
0= Fixed priority
Reserved, write 0's to these bits
0008h
DMA command register 1
DMA Command Register 1
The DMACMD2 register is used to select the type of DRQn and /EOP sampling used,
and to assign a particular bus request to the lowest priority level.
REGISTER:
ADDRESS:
AT ADDRESS:
ACCESS:
D7
D6
D5
D4
D3
D2
D1
D0
---
W/O
1= Sample /DRQn synchronously
0= Sample /DRQn asynchronously
Low priority level set
00= Assign channel 0's request (DRQ0) to the lowest priority level
Reserved
DMACMD2
0F01Ah
DMA command register 2
Reserved
0
0
0
1= Sample /EOP synchronously
0= Sample /EOP asynchronously
01= Assign channel 1's request (DRQ1) to the lowest priority level
10= Assign HOLD to the lowest priority level (RESET state)
11= Reserved
DMA Command Register 2
