Ziatech Corporation ZT 89CT04, Hardware User Manual

Page: 62 / 149

6. DMA Controller
62
REGISTER:
ADDRESS:
AT ADDRESS:
ACCESS:
D7 D6 D5 D4 D3 D2 D1 D0
DMA1BYC2
0F099h
R/W
Channel 1 byte count bit 16
Channel 1 byte count bit 17
Channel 1 byte count bit 18
Channel 1 byte count bit 19
Channel 1 byte count bit 20
Channel 1 byte count bit 21
Channel 1 byte count bit 22
Channel 1 byte count bit 23
ND ND ND ND ND ND ND ND
Channel 1 byte count bits 16-23
---
Channel 1 Byte Count Bits 16-23
DMA Status Register
The DMASTS register is used to check channel status individually. The DMA controller
sets bits in this register to indicate that a channel has a hardware request pending or
that a channel’s byte count has expired.
REGISTER:
ADDRESS:
AT ADDRESS:
ACCESS:
D7 D6 D5 D4 D3 D2
D1
D0
DMASTS
0F008h
R/O
1= Channel 0 transfer complete, read this register to clear this bit
1= Channel 1 transfer complete, read this register to clear this bit
Reserved
Reserved
Reserved 0
0
Reserved 0 0
0= Transfer not completed
0= Transfer not completed
1= Channel 0 has a hardware request pending
0= No hardware request pending for channel 0
1= Channel 1 has a hardware request pending
0= No hardware request pending for channel 1
0008h
DMA status register
DMA Status Register