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12. WATCHDOG TIMER
The primary function of the watchdog timer is to monitor ZT 8904 operation and take
corrective action if the system fails to function as programmed. The major features of
the watchdog timer are listed below.
•
Single-stage or two-stage operation
•
Enabled and disabled through software control
•
Armed and strobed through software control
WATCHDOG TIMER OPERATION
The watchdog timer architecture is illustrated in the "
Watchdog Timer Architecture
"
figure. The first stage is implemented in the Intel 386 EX CPU and the second stage is
implemented in the Dallas Semiconductor DS1236 system monitor.
After power on or reset, the output of the first stage latch is a logical one, which enables
the 8 MHz signal to strobe the second stage. Also after power on or reset, the first stage
begins counting down. After the first stage counts down to zero, a non-maskable
interrupt is generated and the second stage begins counting down.
Jumper W11 must be installed to generate a non-maskable interrupt. Bit 1 of System
Register 0 (7Bh) must be programmed with a logical one to enable the second stage to
begin counting. After the second stage counts down to zero, a reset is generated. If the
ZT 8904 is configured as a permanent master, the reset extends to the STD Bus. If the
ZT 8904 is configured as a temporary master, the reset remains local.
The CPU watchdog timer must be disabled or periodically programmed with a new
count to prevent the first stage from counting to zero. The first stage watchdog timer is
based on a 32-bit counter clocked with a 25 MHz clock. The first stage watchdog
registers are described in the following topic.
After power on or reset the first stage will count to zero after 2.6 ms (64K clock cycles *
40 ns per clock). The first stage is automatically disabled in idle mode. The first stage is
also automatically disabled by the system BIOS in a Ziatech system with DOS.
The non-maskable interrupt service routine must program bit 1 of System Register 0
(7Bh) with a logical zero followed by a logical one to prevent the second stage from
counting to zero. The second stage timeout period is fixed at 100 ms minimum and
600 ms maximum. This means that the non-maskable interrupt service routine must
strobe the second stage within 100 ms to guarantee that a reset does not occur.
