12. Watchdog Timer
101
Watchdog Timer Clear Register
The Watchdog Timer Clear register is programmed with a lockout sequence to enable
watchdog timer mode and to reload the counter. The lockout sequence is shown below.
•
Word write of F01Eh to F4C8h
•
Word write of 0FE1h to F4C8h
7
6
5
4
3
2
1
0
Word Write Sequence
1. F01Eh
2. 0FE1h
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
Register: Watchdog Clear
Address: F4C8h
Access: Write Only
-
-
-
-
-
-
-
-
Watchdog Timer Clear Register
Watchdog Timer Status Register
The Watchdog Timer Status register contains a status bit that is automatically set after a
lockout sequence to indicate that the watchdog timer is active. The status bit is cleared
until the next reset or power cycle.
Register:
Access:
Address:
7
6
5
4
3
2
1
0
-
-
-
-
-
WDT Status
F4CAh
Read
Watchdog State
0= Disable
1= Enable
WEN
0
0
Watchdog Timer Status Register
